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<a href="#nested-classes">Data Structures</a> &#124;
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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>This is the main header file for Xilinx HDMI RX core. </p>
<p>HDMI RX core is used for extracting the video and audio streams from HDMI stream. It consists of</p>
<ul>
<li>Receiver core</li>
<li>AXI4-Stream to Video Bridge</li>
<li>Video Timing Controller and</li>
<li>High-bandwidth Digital Content Protection (HDCP) (Optional)</li>
<li>Data Recovery Unit (DRU) (Optional).</li>
</ul>
<p>Receiver core performs following operations:</p>
<ul>
<li>Aligns incoming data stream to the word boundary and removes inter channel skew.</li>
<li>Unscrambles the data if data rates above the 3.4 Gps. Otherwise bypasses the Scrambler.</li>
<li>Splits the data stream into video and packet data streams.</li>
<li>Optional data streams decrypt by an external HDCP module.</li>
<li>Decodes TMDS data into video data.</li>
<li>Converts the pixel data from the link domain into the video domain.</li>
</ul>
<p>AXI Video Bridge converts the captured native video to AXI stream and outputs the video data through the AXI video interface.</p>
<p>Video Timing Controller (VTC) measures the video timing.</p>
<p>Data Recovery Unit (DRU) to recover the data from the HDMI stream if incoming HDMI stream is too slow for the transceiver.</p>
<p><b>Core Features </b></p>
<p>For a full description of HDMI RX features, please see the hardware specification.</p>
<p><b>Software Initialization &amp; Configuration</b></p>
<p>The application needs to do following steps in order for preparing the HDMI RX core to be ready.</p>
<ul>
<li>Call XV_HdmiRx1_LookupConfig using a device ID to find the core configuration.</li>
<li>Call XV_HdmiRx1_CfgInitialize to initialize the device and the driver instance associated with it.</li>
</ul>
<p><b>Interrupts </b></p>
<p>This driver provides interrupt handlers</p>
<ul>
<li>XV_HdmiRx1_IntrHandler, for handling the interrupts from the HDMI RX core peripherals.</li>
</ul>
<p>Application developer needs to register interrupt handler with the processor, within their examples. Whenever processor calls registered application's interrupt handler associated with interrupt id, application's interrupt handler needs to call appropriate peripheral interrupt handler reading peripheral's Status register.</p>
<p>This driver provides XV_HdmiRx1_SetCallback API to register functions with HDMI RX core instance.</p>
<p><b> Virtual Memory </b></p>
<p>This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.</p>
<p><b> Threads </b></p>
<p>This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.</p>
<p><b> Asserts </b></p>
<p>Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.</p>
<p><b> Building the driver </b></p>
<p>The HDMI RX driver is composed of several source files. This allows the user to build and link only those parts of the driver that are necessary.</p>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who    Date     Changes
</p>
<hr/>
<p>
1.00  EB     02/05/19 Initial release.
</pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx1___config.html">XV_HdmiRx1_Config</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains configuration information for the HDMI RX core.  <a href="struct_x_v___hdmi_rx1___config.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx1___audio_stream.html">XV_HdmiRx1_AudioStream</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains HDMI RX audio stream specific data structure.  <a href="struct_x_v___hdmi_rx1___audio_stream.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx1___stream.html">XV_HdmiRx1_Stream</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains HDMI RX stream specific data structure.  <a href="struct_x_v___hdmi_rx1___stream.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx1___dyn_h_d_r___info.html">XV_HdmiRx1_DynHDR_Info</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains HDMI RX stream specific Dynamic HDR info.  <a href="struct_x_v___hdmi_rx1___dyn_h_d_r___info.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The XHdmiRx1 driver instance data.  <a href="struct_x_v___hdmi_rx1.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:a8462f36d547b076654cb9cb5cd41a57f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a8462f36d547b076654cb9cb5cd41a57f">XV_HDMIRX1_H_</a></td></tr>
<tr class="memdesc:a8462f36d547b076654cb9cb5cd41a57f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="#a8462f36d547b076654cb9cb5cd41a57f">More...</a><br/></td></tr>
<tr class="separator:a8462f36d547b076654cb9cb5cd41a57f"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="enum-members"></a>
Enumerations</h2></td></tr>
<tr><td colspan="2"><div class="groupHeader">Handler Types</div></td></tr>
<tr class="memitem:abbfb262ec57764dd666d070dbda26942"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942">XV_HdmiRx1_HandlerType</a> { <br/>
&#160;&#160;<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a9b4c4aa468273738a419e39c05f0baad">XV_HDMIRX1_HANDLER_CONNECT</a> = 1, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942aebb0160b6b43a4f4e859f45e017faa34">XV_HDMIRX1_HANDLER_BRDG_OVERFLOW</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942adc98639f1c812cd5a2a72f8cac74c868">XV_HDMIRX1_HANDLER_AUX</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942aa481e1b0c381c69e68f4a336c4f4291a">XV_HDMIRX1_HANDLER_AUD</a>, 
<br/>
&#160;&#160;<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a7a01589f01cadd752b2d205f643756b8">XV_HDMIRX1_HANDLER_LNKSTA</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942aff8d61798f42199bedb5c4ccce598ff2">XV_HDMIRX1_HANDLER_DDC</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a0433f28ecdfbbaa25be35be1a1864320">XV_HDMIRX1_HANDLER_STREAM_DOWN</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a4759661b3e3b5ec737b4f42194e1c102">XV_HDMIRX1_HANDLER_STREAM_INIT</a>, 
<br/>
&#160;&#160;<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a79eb6929b21502e375b3621268df1ead">XV_HDMIRX1_HANDLER_STREAM_UP</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a712a8fe2d8cbaa4d6f30a9a34844f1d9">XV_HDMIRX1_HANDLER_HDCP</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942aa0db97ee67a4f31597b3418b6e988338">XV_HDMIRX1_HANDLER_DDC_HDCP_14_PROT</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942aa9498efdb463dd326e02e578db4e6871">XV_HDMIRX1_HANDLER_DDC_HDCP_22_PROT</a>, 
<br/>
&#160;&#160;<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a39fd4542c7878df53d3bf3d18d6762a2">XV_HDMIRX1_HANDLER_LINK_ERROR</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942af9cf2bdb04e25e90100885f80be68d12">XV_HDMIRX1_HANDLER_SYNC_LOSS</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942ae118085eb55b228455f78663cb661a27">XV_HDMIRX1_HANDLER_MODE</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a2c3b39213e1ef49751a14777963398d5">XV_HDMIRX1_HANDLER_TMDS_CLK_RATIO</a>, 
<br/>
&#160;&#160;<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a314a6cd00e81397687bdda8b4f073768">XV_HDMIRX1_HANDLER_VIC_ERROR</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a6ab6e9177942ae3f4bd6ed8bfa5873b6">XV_HDMIRX1_HANDLER_PHY_RESET</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a03722585c04e5e62c80b912854856f31">XV_HDMIRX1_HANDLER_LNK_RDY_ERR</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a73d3498284bf4989a39e48a55146abf3">XV_HDMIRX1_HANDLER_VID_RDY_ERR</a>, 
<br/>
&#160;&#160;<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a9f4c993efb8541e185ba312968e89d93">XV_HDMIRX1_HANDLER_SKEW_LOCK_ERR</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942aff9bf32f7a33b804800d8d5706986fd9">XV_HDMIRX1_HANDLER_FRL_CONFIG</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942ab0d40648a4270a90b8816085080c2dc4">XV_HDMIRX1_HANDLER_FRL_START</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a19d8897bb48beef6cc192dce8e656224">XV_HDMIRX1_HANDLER_TMDS_CONFIG</a>
, <br/>
&#160;&#160;<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a9b60139f3a0336b0e920ab5dd18dc183">XV_HDMIRX1_HANDLER_VFP_CHANGE</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a19a71662e67c08479b6f24a6c6930be7">XV_HDMIRX1_HANDLER_VRR_RDY</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a6c6dec8c2000bd56980e104718de20b8">XV_HDMIRX1_HANDLER_DYN_HDR</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942ae440e854baa6be9065fa24b541a211a8">XV_HDMIRX1_HANDLER_DSC_STRM_CH</a>, 
<br/>
&#160;&#160;<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942abd439ec152f3be928e4b1a78f6e462f8">XV_HDMIRX1_HANDLER_DSC_PKT_ERR</a>, 
<a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a7e57e5a185607118363c0a8d86b20c6d">XV_HDMIRX1_HANDLER_DSC_STS_UPDT</a>
<br/>
 }</td></tr>
<tr class="memdesc:abbfb262ec57764dd666d070dbda26942"><td class="mdescLeft">&#160;</td><td class="mdescRight">These constants specify different types of handler and used to differentiate interrupt requests from peripheral.  <a href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942">More...</a><br/></td></tr>
<tr class="separator:abbfb262ec57764dd666d070dbda26942"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">HDMI RX stream status</div></td></tr>
<tr class="memitem:aaff80d21f94c4b494ab6beb909f74eba"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#aaff80d21f94c4b494ab6beb909f74eba">XV_HdmiRx1_State</a> { , <br/>
&#160;&#160;<a class="el" href="xv__hdmirx1_8h.html#aaff80d21f94c4b494ab6beb909f74ebaa9b3b6fc66356c86b1e37dc20b4a69933">XV_HDMIRX1_STATE_STREAM_DOWN</a>, 
<a class="el" href="xv__hdmirx1_8h.html#aaff80d21f94c4b494ab6beb909f74ebaaa1f34d784d248ada4547ce9c98d6fb0c">XV_HDMIRX1_STATE_STREAM_IDLE</a>, 
<a class="el" href="xv__hdmirx1_8h.html#aaff80d21f94c4b494ab6beb909f74ebaa951d06813050d87c5939cfaaced6e8df">XV_HDMIRX1_STATE_STREAM_INIT</a>, 
<a class="el" href="xv__hdmirx1_8h.html#aaff80d21f94c4b494ab6beb909f74ebaa9809e0d6666c90f18ac68d18aa56f46f">XV_HDMIRX1_STATE_STREAM_ARM</a>, 
<br/>
&#160;&#160;<a class="el" href="xv__hdmirx1_8h.html#aaff80d21f94c4b494ab6beb909f74ebaad8dee1d15d52d9c72cb69452261e3104">XV_HDMIRX1_STATE_STREAM_LOCK</a>, 
<a class="el" href="xv__hdmirx1_8h.html#aaff80d21f94c4b494ab6beb909f74ebaa68f8ec479e8bdfc98649a9bfde2405a7">XV_HDMIRX1_STATE_STREAM_RDY</a>, 
<a class="el" href="xv__hdmirx1_8h.html#aaff80d21f94c4b494ab6beb909f74ebaa78cc6e34272e81a858d62f92557a3950">XV_HDMIRX1_STATE_STREAM_UP</a>
<br/>
 }</td></tr>
<tr class="separator:aaff80d21f94c4b494ab6beb909f74eba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">HDMI RX sync status</div></td></tr>
<tr class="memitem:a78b0c5167ed122389fed2d59f379a775"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a78b0c5167ed122389fed2d59f379a775">XV_HdmiRx1_SyncStatus</a> { <a class="el" href="xv__hdmirx1_8h.html#a78b0c5167ed122389fed2d59f379a775a01cffeb117a47b14208e30c8dd82ee24">XV_HDMIRX1_SYNCSTAT_SYNC_LOSS</a>, 
<a class="el" href="xv__hdmirx1_8h.html#a78b0c5167ed122389fed2d59f379a775a2f310f02db1fab96adfecbb7d4a47070">XV_HDMIRX1_SYNCSTAT_SYNC_EST</a>
 }</td></tr>
<tr class="separator:a78b0c5167ed122389fed2d59f379a775"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">HDMI RX audio format</div></td></tr>
<tr class="memitem:a0cb25172092121e6869edaabb46d0d43"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiRx1_AudioFormatType</b> </td></tr>
<tr class="separator:a0cb25172092121e6869edaabb46d0d43"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">HDMI RX EDID RAM Size</div></td></tr>
<tr class="memitem:a57e6477754dd3efaa2bf2401de7621fc"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiRx1_EdidSize</b> </td></tr>
<tr class="separator:a57e6477754dd3efaa2bf2401de7621fc"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
HDMI RX Dynamic HDR Error type</h2></td></tr>
<tr class="memitem:a538f6978102edb024555a3bb35e56af2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a538f6978102edb024555a3bb35e56af2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>TIME_10MS</b>&#160;&#160;&#160;(XPAR_XV_HDMIRX1_0_AXI_LITE_FREQ_HZ/100)</td></tr>
<tr class="separator:a538f6978102edb024555a3bb35e56af2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad54e9da64211cd4fe074da1a8a736a9a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad54e9da64211cd4fe074da1a8a736a9a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>TIME_200MS</b>&#160;&#160;&#160;(XPAR_XV_HDMIRX1_0_AXI_LITE_FREQ_HZ/5)</td></tr>
<tr class="separator:ad54e9da64211cd4fe074da1a8a736a9a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1281376ea775dcac0b2d63413d57b9e5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1281376ea775dcac0b2d63413d57b9e5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>TIME_16MS</b>&#160;&#160;&#160;((XPAR_XV_HDMIRX1_0_AXI_LITE_FREQ_HZ*10)/625)</td></tr>
<tr class="separator:a1281376ea775dcac0b2d63413d57b9e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a600f7970cb82f915b8a97953f6d76bca"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a600f7970cb82f915b8a97953f6d76bca"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>TIME_500MS</b>&#160;&#160;&#160;(XPAR_XV_HDMIRX1_0_AXI_LITE_FREQ_HZ / 2)</td></tr>
<tr class="separator:a600f7970cb82f915b8a97953f6d76bca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a81fe9e2cecb6b2c872862de8afe96115"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a81fe9e2cecb6b2c872862de8afe96115">XV_HdmiRx1_GetTime10Ms</a>(InstancePtr)&#160;&#160;&#160;(InstancePtr)-&gt;Config.AxiLiteClkFreq/100</td></tr>
<tr class="memdesc:a81fe9e2cecb6b2c872862de8afe96115"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro returns the clock cycles required to count up to 10Ms with respect to AXI Lite Frequency.  <a href="#a81fe9e2cecb6b2c872862de8afe96115">More...</a><br/></td></tr>
<tr class="separator:a81fe9e2cecb6b2c872862de8afe96115"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab5713966b53828111f26a3a75e0e8d1a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ab5713966b53828111f26a3a75e0e8d1a">XV_HdmiRx1_GetTime16Ms</a>(InstancePtr)&#160;&#160;&#160;((InstancePtr)-&gt;Config.AxiLiteClkFreq * 10) / 625</td></tr>
<tr class="memdesc:ab5713966b53828111f26a3a75e0e8d1a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro returns the clock cycles required to count up to 16Ms with respect to AXI Lite Frequency.  <a href="#ab5713966b53828111f26a3a75e0e8d1a">More...</a><br/></td></tr>
<tr class="separator:ab5713966b53828111f26a3a75e0e8d1a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac4d147dab9255ea47ee7c5e5f9a45a7e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ac4d147dab9255ea47ee7c5e5f9a45a7e">XV_HdmiRx1_GetTime200Ms</a>(InstancePtr)&#160;&#160;&#160;(InstancePtr)-&gt;Config.AxiLiteClkFreq/5</td></tr>
<tr class="memdesc:ac4d147dab9255ea47ee7c5e5f9a45a7e"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro returns the clock cycles required to count up to 200Ms with respect to AXI Lite Frequency.  <a href="#ac4d147dab9255ea47ee7c5e5f9a45a7e">More...</a><br/></td></tr>
<tr class="separator:ac4d147dab9255ea47ee7c5e5f9a45a7e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af5225d7549628e39d200cb5d6f0ef44a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#af5225d7549628e39d200cb5d6f0ef44a">XV_HdmiRx1_GetTime1S</a>(InstancePtr)&#160;&#160;&#160;(InstancePtr)-&gt;Config.AxiLiteClkFreq</td></tr>
<tr class="memdesc:af5225d7549628e39d200cb5d6f0ef44a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro returns the clock cycles required to count up to 1s with respect to AXI Lite Frequency.  <a href="#af5225d7549628e39d200cb5d6f0ef44a">More...</a><br/></td></tr>
<tr class="separator:af5225d7549628e39d200cb5d6f0ef44a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2c43beaac345faea28b787d8c40e5741"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a2c43beaac345faea28b787d8c40e5741">XV_HdmiRx1_GetVersion</a>(InstancePtr)</td></tr>
<tr class="memdesc:a2c43beaac345faea28b787d8c40e5741"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads the RX version.  <a href="#a2c43beaac345faea28b787d8c40e5741">More...</a><br/></td></tr>
<tr class="separator:a2c43beaac345faea28b787d8c40e5741"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a33e7dd96086ade48b9cf40729dc5e997"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a33e7dd96086ade48b9cf40729dc5e997">XV_HdmiRx1_Reset</a>(InstancePtr, Reset)</td></tr>
<tr class="memdesc:a33e7dd96086ade48b9cf40729dc5e997"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro asserts or clears the HDMI RX reset.  <a href="#a33e7dd96086ade48b9cf40729dc5e997">More...</a><br/></td></tr>
<tr class="separator:a33e7dd96086ade48b9cf40729dc5e997"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a760bfb529cffa6770d3c27d81d02adab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a760bfb529cffa6770d3c27d81d02adab">XV_HdmiRx1_LinkEnable</a>(InstancePtr, SetClr)</td></tr>
<tr class="memdesc:a760bfb529cffa6770d3c27d81d02adab"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro asserts or clears the HDMI RX link enable.  <a href="#a760bfb529cffa6770d3c27d81d02adab">More...</a><br/></td></tr>
<tr class="separator:a760bfb529cffa6770d3c27d81d02adab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a79fe6ac6968f75dab49b5327aa3995e9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a79fe6ac6968f75dab49b5327aa3995e9">XV_HdmiRx1_VideoEnable</a>(InstancePtr, SetClr)</td></tr>
<tr class="memdesc:a79fe6ac6968f75dab49b5327aa3995e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro asserts or clears the HDMI RX video enable.  <a href="#a79fe6ac6968f75dab49b5327aa3995e9">More...</a><br/></td></tr>
<tr class="separator:a79fe6ac6968f75dab49b5327aa3995e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3b0e4a6f27c287db2e8876157c1675ee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a3b0e4a6f27c287db2e8876157c1675ee">XV_HdmiRx1_SetScrambler</a>(InstancePtr, SetClr)</td></tr>
<tr class="memdesc:a3b0e4a6f27c287db2e8876157c1675ee"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro controls the HDMI RX Scrambler.  <a href="#a3b0e4a6f27c287db2e8876157c1675ee">More...</a><br/></td></tr>
<tr class="separator:a3b0e4a6f27c287db2e8876157c1675ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8b431f0a256aba088876a8137c47400c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a8b431f0a256aba088876a8137c47400c">XV_HdmiRx1_Bridge_yuv420</a>(InstancePtr, SetClr)</td></tr>
<tr class="memdesc:a8b431f0a256aba088876a8137c47400c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro controls the YUV420 mode for video bridge.  <a href="#a8b431f0a256aba088876a8137c47400c">More...</a><br/></td></tr>
<tr class="separator:a8b431f0a256aba088876a8137c47400c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2b959c8cce4d462ec624a59d1aa6802c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a2b959c8cce4d462ec624a59d1aa6802c">XV_HdmiRx1_Bridge_pixel</a>(InstancePtr, SetClr)</td></tr>
<tr class="memdesc:a2b959c8cce4d462ec624a59d1aa6802c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro controls the Pixel Drop mode for video bridge.  <a href="#a2b959c8cce4d462ec624a59d1aa6802c">More...</a><br/></td></tr>
<tr class="separator:a2b959c8cce4d462ec624a59d1aa6802c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a536f7ca1bc870452a33d8bf7fa54eb17"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a536f7ca1bc870452a33d8bf7fa54eb17">XV_HdmiRx1_AxisEnable</a>(InstancePtr, Enable)</td></tr>
<tr class="memdesc:a536f7ca1bc870452a33d8bf7fa54eb17"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro asserts or clears the AXIS enable output port.  <a href="#a536f7ca1bc870452a33d8bf7fa54eb17">More...</a><br/></td></tr>
<tr class="separator:a536f7ca1bc870452a33d8bf7fa54eb17"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab1af2cce1f2ff3ae52dfb4cfbcd9a436"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ab1af2cce1f2ff3ae52dfb4cfbcd9a436">XV_HdmiRx1_PioEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:ab1af2cce1f2ff3ae52dfb4cfbcd9a436"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables the HDMI RX PIO peripheral.  <a href="#ab1af2cce1f2ff3ae52dfb4cfbcd9a436">More...</a><br/></td></tr>
<tr class="separator:ab1af2cce1f2ff3ae52dfb4cfbcd9a436"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4d57a91b21377a43a2692f64564bc121"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a4d57a91b21377a43a2692f64564bc121">XV_HdmiRx1_PioDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a4d57a91b21377a43a2692f64564bc121"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables the HDMI RX PIO peripheral.  <a href="#a4d57a91b21377a43a2692f64564bc121">More...</a><br/></td></tr>
<tr class="separator:a4d57a91b21377a43a2692f64564bc121"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5ec3cb1a32c4e030d365023832bba3e2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a5ec3cb1a32c4e030d365023832bba3e2">XV_HdmiRx1_PioIntrEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a5ec3cb1a32c4e030d365023832bba3e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables interrupts in the HDMI RX PIO peripheral.  <a href="#a5ec3cb1a32c4e030d365023832bba3e2">More...</a><br/></td></tr>
<tr class="separator:a5ec3cb1a32c4e030d365023832bba3e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae5f391082b5e60a7ea25086124900070"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ae5f391082b5e60a7ea25086124900070">XV_HdmiRx1_PioIntrDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:ae5f391082b5e60a7ea25086124900070"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables interrupts in the HDMI RX PIO peripheral.  <a href="#ae5f391082b5e60a7ea25086124900070">More...</a><br/></td></tr>
<tr class="separator:ae5f391082b5e60a7ea25086124900070"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a056971e8df07e73576859f1d25eb5b96"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a056971e8df07e73576859f1d25eb5b96">XV_HdmiRx1_Tmr1Enable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a056971e8df07e73576859f1d25eb5b96"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables the HDMI RX timer peripheral.  <a href="#a056971e8df07e73576859f1d25eb5b96">More...</a><br/></td></tr>
<tr class="separator:a056971e8df07e73576859f1d25eb5b96"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aec115cc3973ecedde65e4b11d3ad5b5b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#aec115cc3973ecedde65e4b11d3ad5b5b">XV_HdmiRx1_Tmr1Disable</a>(InstancePtr)</td></tr>
<tr class="memdesc:aec115cc3973ecedde65e4b11d3ad5b5b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables the HDMI RX timer peripheral.  <a href="#aec115cc3973ecedde65e4b11d3ad5b5b">More...</a><br/></td></tr>
<tr class="separator:aec115cc3973ecedde65e4b11d3ad5b5b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a27d61d0271f92f32b92971dcd726c2ca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a27d61d0271f92f32b92971dcd726c2ca">XV_HdmiRx1_Tmr1IntrEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a27d61d0271f92f32b92971dcd726c2ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables interrupts in the HDMI RX timer peripheral.  <a href="#a27d61d0271f92f32b92971dcd726c2ca">More...</a><br/></td></tr>
<tr class="separator:a27d61d0271f92f32b92971dcd726c2ca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a267240b43d2cadda19be932109867557"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a267240b43d2cadda19be932109867557">XV_HdmiRx1_Tmr1IntrDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a267240b43d2cadda19be932109867557"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables interrupt in the HDMI RX timer peripheral.  <a href="#a267240b43d2cadda19be932109867557">More...</a><br/></td></tr>
<tr class="separator:a267240b43d2cadda19be932109867557"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aaa7bbaf2ae1157d275c4963c2f11cd16"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#aaa7bbaf2ae1157d275c4963c2f11cd16">XV_HdmiRx1_Tmr1Start</a>(InstancePtr, Value)</td></tr>
<tr class="memdesc:aaa7bbaf2ae1157d275c4963c2f11cd16"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro starts the HDMI RX timer peripheral.  <a href="#aaa7bbaf2ae1157d275c4963c2f11cd16">More...</a><br/></td></tr>
<tr class="separator:aaa7bbaf2ae1157d275c4963c2f11cd16"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7de25fdf8166abb9ae7a4f9a3d7b5555"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a7de25fdf8166abb9ae7a4f9a3d7b5555">XV_HdmiRx1_GetTmr1Value</a>(InstancePtr)</td></tr>
<tr class="memdesc:a7de25fdf8166abb9ae7a4f9a3d7b5555"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads the HDMI RX timer peripheral's remaining timer counter value.  <a href="#a7de25fdf8166abb9ae7a4f9a3d7b5555">More...</a><br/></td></tr>
<tr class="separator:a7de25fdf8166abb9ae7a4f9a3d7b5555"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a015741105c8cf02b20e69e03b65ccc71"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a015741105c8cf02b20e69e03b65ccc71">XV_HdmiRx1_Tmr2Enable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a015741105c8cf02b20e69e03b65ccc71"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables the HDMI RX timer peripheral.  <a href="#a015741105c8cf02b20e69e03b65ccc71">More...</a><br/></td></tr>
<tr class="separator:a015741105c8cf02b20e69e03b65ccc71"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1faa4df9824550b8f828d68597ddd2c1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a1faa4df9824550b8f828d68597ddd2c1">XV_HdmiRx1_Tmr2Disable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a1faa4df9824550b8f828d68597ddd2c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables the HDMI RX timer peripheral.  <a href="#a1faa4df9824550b8f828d68597ddd2c1">More...</a><br/></td></tr>
<tr class="separator:a1faa4df9824550b8f828d68597ddd2c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac88f46543d066f90f95e6ca05e9561de"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ac88f46543d066f90f95e6ca05e9561de">XV_HdmiRx1_Tmr2IntrEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:ac88f46543d066f90f95e6ca05e9561de"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables interrupts in the HDMI RX timer peripheral.  <a href="#ac88f46543d066f90f95e6ca05e9561de">More...</a><br/></td></tr>
<tr class="separator:ac88f46543d066f90f95e6ca05e9561de"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af026514eac245f4f7fea082361577997"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#af026514eac245f4f7fea082361577997">XV_HdmiRx1_Tmr2IntrDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:af026514eac245f4f7fea082361577997"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables interrupt in the HDMI RX timer peripheral.  <a href="#af026514eac245f4f7fea082361577997">More...</a><br/></td></tr>
<tr class="separator:af026514eac245f4f7fea082361577997"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab2b8c0c606b059fe056a78b9a93417b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ab2b8c0c606b059fe056a78b9a93417b8">XV_HdmiRx1_Tmr2Start</a>(InstancePtr, Value)</td></tr>
<tr class="memdesc:ab2b8c0c606b059fe056a78b9a93417b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro starts the HDMI RX timer peripheral.  <a href="#ab2b8c0c606b059fe056a78b9a93417b8">More...</a><br/></td></tr>
<tr class="separator:ab2b8c0c606b059fe056a78b9a93417b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab35c7e83b036ed9da616b6493f37cf74"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ab35c7e83b036ed9da616b6493f37cf74">XV_HdmiRx1_GetTmr2Value</a>(InstancePtr)</td></tr>
<tr class="memdesc:ab35c7e83b036ed9da616b6493f37cf74"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads the HDMI RX timer peripheral's remaining timer counter value.  <a href="#ab35c7e83b036ed9da616b6493f37cf74">More...</a><br/></td></tr>
<tr class="separator:ab35c7e83b036ed9da616b6493f37cf74"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7a1da40034b17fcdd3a0b4e62d17cf78"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a7a1da40034b17fcdd3a0b4e62d17cf78">XV_HdmiRx1_Tmr3Enable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a7a1da40034b17fcdd3a0b4e62d17cf78"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables the HDMI RX timer peripheral.  <a href="#a7a1da40034b17fcdd3a0b4e62d17cf78">More...</a><br/></td></tr>
<tr class="separator:a7a1da40034b17fcdd3a0b4e62d17cf78"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aadacbe89d70bbefbf1e71042d777ea92"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#aadacbe89d70bbefbf1e71042d777ea92">XV_HdmiRx1_Tmr3Disable</a>(InstancePtr)</td></tr>
<tr class="memdesc:aadacbe89d70bbefbf1e71042d777ea92"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables the HDMI RX timer peripheral.  <a href="#aadacbe89d70bbefbf1e71042d777ea92">More...</a><br/></td></tr>
<tr class="separator:aadacbe89d70bbefbf1e71042d777ea92"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a826103168347fef524be56f819b48b2d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a826103168347fef524be56f819b48b2d">XV_HdmiRx1_Tmr3IntrEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a826103168347fef524be56f819b48b2d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables interrupts in the HDMI RX timer peripheral.  <a href="#a826103168347fef524be56f819b48b2d">More...</a><br/></td></tr>
<tr class="separator:a826103168347fef524be56f819b48b2d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a963af2bc8daca1f5f771b75e7ed0f83d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a963af2bc8daca1f5f771b75e7ed0f83d">XV_HdmiRx1_Tmr3IntrDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a963af2bc8daca1f5f771b75e7ed0f83d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables interrupt in the HDMI RX timer peripheral.  <a href="#a963af2bc8daca1f5f771b75e7ed0f83d">More...</a><br/></td></tr>
<tr class="separator:a963af2bc8daca1f5f771b75e7ed0f83d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0b54de6bbd95ea2f25998c28db0fef69"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a0b54de6bbd95ea2f25998c28db0fef69">XV_HdmiRx1_Tmr3Start</a>(InstancePtr, Value)</td></tr>
<tr class="memdesc:a0b54de6bbd95ea2f25998c28db0fef69"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro starts the HDMI RX timer peripheral.  <a href="#a0b54de6bbd95ea2f25998c28db0fef69">More...</a><br/></td></tr>
<tr class="separator:a0b54de6bbd95ea2f25998c28db0fef69"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abe903d75443ce36e9868f719091ebb05"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#abe903d75443ce36e9868f719091ebb05">XV_HdmiRx1_GetTmr3Value</a>(InstancePtr)</td></tr>
<tr class="memdesc:abe903d75443ce36e9868f719091ebb05"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads the HDMI RX timer peripheral's remaining timer counter value.  <a href="#abe903d75443ce36e9868f719091ebb05">More...</a><br/></td></tr>
<tr class="separator:abe903d75443ce36e9868f719091ebb05"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab3f9e1b5c62459aca4117b574e97cb20"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ab3f9e1b5c62459aca4117b574e97cb20">XV_HdmiRx1_Tmr4Enable</a>(InstancePtr)</td></tr>
<tr class="memdesc:ab3f9e1b5c62459aca4117b574e97cb20"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables the HDMI RX timer peripheral.  <a href="#ab3f9e1b5c62459aca4117b574e97cb20">More...</a><br/></td></tr>
<tr class="separator:ab3f9e1b5c62459aca4117b574e97cb20"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1bbae2cd92459ab09caba931c2eeb766"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a1bbae2cd92459ab09caba931c2eeb766">XV_HdmiRx1_Tmr4Disable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a1bbae2cd92459ab09caba931c2eeb766"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables the HDMI RX timer peripheral.  <a href="#a1bbae2cd92459ab09caba931c2eeb766">More...</a><br/></td></tr>
<tr class="separator:a1bbae2cd92459ab09caba931c2eeb766"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a62815abff227bdf3168089698b368a9b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a62815abff227bdf3168089698b368a9b">XV_HdmiRx1_Tmr4IntrEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a62815abff227bdf3168089698b368a9b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables interrupts in the HDMI RX timer peripheral.  <a href="#a62815abff227bdf3168089698b368a9b">More...</a><br/></td></tr>
<tr class="separator:a62815abff227bdf3168089698b368a9b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a142ca05b75d070d95c61004b82bb5a68"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a142ca05b75d070d95c61004b82bb5a68">XV_HdmiRx1_Tmr4IntrDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a142ca05b75d070d95c61004b82bb5a68"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables interrupt in the HDMI RX timer peripheral.  <a href="#a142ca05b75d070d95c61004b82bb5a68">More...</a><br/></td></tr>
<tr class="separator:a142ca05b75d070d95c61004b82bb5a68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4de4494c309d24995f84a567459d7b31"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a4de4494c309d24995f84a567459d7b31">XV_HdmiRx1_Tmr4Start</a>(InstancePtr, Value)</td></tr>
<tr class="memdesc:a4de4494c309d24995f84a567459d7b31"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro starts the HDMI RX timer peripheral.  <a href="#a4de4494c309d24995f84a567459d7b31">More...</a><br/></td></tr>
<tr class="separator:a4de4494c309d24995f84a567459d7b31"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2138cb9268f7da591da9f9ab73d1e735"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a2138cb9268f7da591da9f9ab73d1e735">XV_HdmiRx1_GetTmr4Value</a>(InstancePtr)</td></tr>
<tr class="memdesc:a2138cb9268f7da591da9f9ab73d1e735"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads the HDMI RX timer peripheral's remaining timer counter value.  <a href="#a2138cb9268f7da591da9f9ab73d1e735">More...</a><br/></td></tr>
<tr class="separator:a2138cb9268f7da591da9f9ab73d1e735"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1ef161f38b2d9108a4923fec0fc880f1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a1ef161f38b2d9108a4923fec0fc880f1">XV_HdmiRx1_VtdEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a1ef161f38b2d9108a4923fec0fc880f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables the HDMI RX Timing Detector peripheral.  <a href="#a1ef161f38b2d9108a4923fec0fc880f1">More...</a><br/></td></tr>
<tr class="separator:a1ef161f38b2d9108a4923fec0fc880f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab5508950e173aa4b8c4736e0ae09266c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ab5508950e173aa4b8c4736e0ae09266c">XV_HdmiRx1_VtdDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:ab5508950e173aa4b8c4736e0ae09266c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables the HDMI RX Timing Detector peripheral.  <a href="#ab5508950e173aa4b8c4736e0ae09266c">More...</a><br/></td></tr>
<tr class="separator:ab5508950e173aa4b8c4736e0ae09266c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af02bc319e791bee6ef832346327dd0be"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#af02bc319e791bee6ef832346327dd0be">XV_HdmiRx1_VtdIntrEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:af02bc319e791bee6ef832346327dd0be"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables interrupt in the HDMI RX Timing Detector peripheral.  <a href="#af02bc319e791bee6ef832346327dd0be">More...</a><br/></td></tr>
<tr class="separator:af02bc319e791bee6ef832346327dd0be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a59b4dbbffb9eeec8b22acc012d22e07f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a59b4dbbffb9eeec8b22acc012d22e07f">XV_HdmiRx1_VtdIntrDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a59b4dbbffb9eeec8b22acc012d22e07f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables interrupt in the HDMI RX Timing Detector peripheral.  <a href="#a59b4dbbffb9eeec8b22acc012d22e07f">More...</a><br/></td></tr>
<tr class="separator:a59b4dbbffb9eeec8b22acc012d22e07f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a922e50f2b67a8bb2db9ed7eda0e8e347"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a922e50f2b67a8bb2db9ed7eda0e8e347">XV_HdmiRx1_VtdVfpEvent</a>(InstancePtr, SetClr)</td></tr>
<tr class="memdesc:a922e50f2b67a8bb2db9ed7eda0e8e347"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro allow control to enable/disable the HDMI RX VFP event.  <a href="#a922e50f2b67a8bb2db9ed7eda0e8e347">More...</a><br/></td></tr>
<tr class="separator:a922e50f2b67a8bb2db9ed7eda0e8e347"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a56b0470904fc7dad8850ce0b88738404"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a56b0470904fc7dad8850ce0b88738404">XV_HdmiRx1_VtdSetTimebase</a>(InstancePtr, Value)</td></tr>
<tr class="memdesc:a56b0470904fc7dad8850ce0b88738404"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro sets the timebase in the HDMI RX Timing Detector peripheral.  <a href="#a56b0470904fc7dad8850ce0b88738404">More...</a><br/></td></tr>
<tr class="separator:a56b0470904fc7dad8850ce0b88738404"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2fa160f04e804a5214822c2031bcce4a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a2fa160f04e804a5214822c2031bcce4a">XV_HdmiRx1_DdcEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a2fa160f04e804a5214822c2031bcce4a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables the HDMI RX Display Data Channel (DDC) peripheral.  <a href="#a2fa160f04e804a5214822c2031bcce4a">More...</a><br/></td></tr>
<tr class="separator:a2fa160f04e804a5214822c2031bcce4a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a29847cccb96616c7a70252a0ae823e67"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a29847cccb96616c7a70252a0ae823e67">XV_HdmiRx1_DdcScdcEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a29847cccb96616c7a70252a0ae823e67"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables the SCDC in the DDC peripheral.  <a href="#a29847cccb96616c7a70252a0ae823e67">More...</a><br/></td></tr>
<tr class="separator:a29847cccb96616c7a70252a0ae823e67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae85e61794d7039e19fe4ed0994af122a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ae85e61794d7039e19fe4ed0994af122a">XV_HdmiRx1_DdcHdcpEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:ae85e61794d7039e19fe4ed0994af122a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables the HDCP in the DDC peripheral.  <a href="#ae85e61794d7039e19fe4ed0994af122a">More...</a><br/></td></tr>
<tr class="separator:ae85e61794d7039e19fe4ed0994af122a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9a709c37f29d4c2f699196c5dd313997"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9a709c37f29d4c2f699196c5dd313997"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiRx1_DdcHdcpDisable</b>(InstancePtr)</td></tr>
<tr class="separator:a9a709c37f29d4c2f699196c5dd313997"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0a1ce2053f275719061d178860e990e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a0a1ce2053f275719061d178860e990e6">XV_HdmiRx1_DdcHdcp14Mode</a>(InstancePtr)</td></tr>
<tr class="memdesc:a0a1ce2053f275719061d178860e990e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro sets the DDC peripheral into HDCP 1.4 mode.  <a href="#a0a1ce2053f275719061d178860e990e6">More...</a><br/></td></tr>
<tr class="separator:a0a1ce2053f275719061d178860e990e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aebc9674ef54135cb579c47b83ea51d56"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#aebc9674ef54135cb579c47b83ea51d56">XV_HdmiRx1_DdcHdcp22Mode</a>(InstancePtr)</td></tr>
<tr class="memdesc:aebc9674ef54135cb579c47b83ea51d56"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro sets the DDC peripheral into HDCP 2.2 mode.  <a href="#aebc9674ef54135cb579c47b83ea51d56">More...</a><br/></td></tr>
<tr class="separator:aebc9674ef54135cb579c47b83ea51d56"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afa5c7f669b19e1b0f9cbad39adb674bc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#afa5c7f669b19e1b0f9cbad39adb674bc">XV_HdmiRx1_DdcDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:afa5c7f669b19e1b0f9cbad39adb674bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables the HDMI RX Display Data Channel (DDC) peripheral.  <a href="#afa5c7f669b19e1b0f9cbad39adb674bc">More...</a><br/></td></tr>
<tr class="separator:afa5c7f669b19e1b0f9cbad39adb674bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1c97d857d2d7737f4c9a25975e6cdab7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a1c97d857d2d7737f4c9a25975e6cdab7">XV_HdmiRx1_DdcIntrEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a1c97d857d2d7737f4c9a25975e6cdab7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables interrupts in the HDMI RX Display Data Channel (DDC) peripheral.  <a href="#a1c97d857d2d7737f4c9a25975e6cdab7">More...</a><br/></td></tr>
<tr class="separator:a1c97d857d2d7737f4c9a25975e6cdab7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a454b5d814587e811db3529121a42dffe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a454b5d814587e811db3529121a42dffe">XV_HdmiRx1_DdcIntrDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a454b5d814587e811db3529121a42dffe"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables interrupts in the HDMI RX Display Data Channel (DDC) peripheral.  <a href="#a454b5d814587e811db3529121a42dffe">More...</a><br/></td></tr>
<tr class="separator:a454b5d814587e811db3529121a42dffe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad2801bbba5e4a3492373d59f783bc0b4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ad2801bbba5e4a3492373d59f783bc0b4">XV_HdmiRx1_DdcScdcClear</a>(InstancePtr)</td></tr>
<tr class="memdesc:ad2801bbba5e4a3492373d59f783bc0b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro clears the SCDC registers in the DDC peripheral.  <a href="#ad2801bbba5e4a3492373d59f783bc0b4">More...</a><br/></td></tr>
<tr class="separator:ad2801bbba5e4a3492373d59f783bc0b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2c5da76a0a84df38663bea3d958bbb40"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a2c5da76a0a84df38663bea3d958bbb40">XV_HdmiRx1_AuxEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a2c5da76a0a84df38663bea3d958bbb40"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables the HDMI RX Auxiliary (AUX) peripheral.  <a href="#a2c5da76a0a84df38663bea3d958bbb40">More...</a><br/></td></tr>
<tr class="separator:a2c5da76a0a84df38663bea3d958bbb40"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab7b551cd29147914edb614a75ad72106"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ab7b551cd29147914edb614a75ad72106">XV_HdmiRx1_AuxDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:ab7b551cd29147914edb614a75ad72106"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables the HDMI RX Auxiliary (AUX) peripheral.  <a href="#ab7b551cd29147914edb614a75ad72106">More...</a><br/></td></tr>
<tr class="separator:ab7b551cd29147914edb614a75ad72106"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af5e8e60bd7c915758d1a6961901427cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#af5e8e60bd7c915758d1a6961901427cc">XV_HdmiRx1_AuxIntrEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:af5e8e60bd7c915758d1a6961901427cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables interrupts in the HDMI RX Auxiliary (AUX) peripheral.  <a href="#af5e8e60bd7c915758d1a6961901427cc">More...</a><br/></td></tr>
<tr class="separator:af5e8e60bd7c915758d1a6961901427cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1795c1a58886dfef4dff8d48d83781f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a1795c1a58886dfef4dff8d48d83781f5">XV_HdmiRx1_AuxIntrDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a1795c1a58886dfef4dff8d48d83781f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables interrupts in the HDMI RX Auxiliary (AUX) peripheral.  <a href="#a1795c1a58886dfef4dff8d48d83781f5">More...</a><br/></td></tr>
<tr class="separator:a1795c1a58886dfef4dff8d48d83781f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a167821ef9d8c222d4d8c1bc194e1d42b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a167821ef9d8c222d4d8c1bc194e1d42b">XV_HdmiRx1_AuxFSyncVrrChEvtEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a167821ef9d8c222d4d8c1bc194e1d42b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables FSync/VRR event interrupt in the HDMI RX Auxiliary (AUX) peripheral.  <a href="#a167821ef9d8c222d4d8c1bc194e1d42b">More...</a><br/></td></tr>
<tr class="separator:a167821ef9d8c222d4d8c1bc194e1d42b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a33ea1831b4176642737b0ab57a821130"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a33ea1831b4176642737b0ab57a821130">XV_HdmiRx1_AuxFSyncVrrChEvtDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a33ea1831b4176642737b0ab57a821130"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables FSync/VRR event interrupt in the HDMI RX Auxiliary (AUX) peripheral.  <a href="#a33ea1831b4176642737b0ab57a821130">More...</a><br/></td></tr>
<tr class="separator:a33ea1831b4176642737b0ab57a821130"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3994fbc415670b527fa40e4b634c9f49"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a3994fbc415670b527fa40e4b634c9f49">XV_HdmiRx1_AudioEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a3994fbc415670b527fa40e4b634c9f49"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables the HDMI RX Audio (AUD) peripheral.  <a href="#a3994fbc415670b527fa40e4b634c9f49">More...</a><br/></td></tr>
<tr class="separator:a3994fbc415670b527fa40e4b634c9f49"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4ddfdbb13a735158eac6316b10fe827b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a4ddfdbb13a735158eac6316b10fe827b">XV_HdmiRx1_AudioDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a4ddfdbb13a735158eac6316b10fe827b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables the HDMI RX Audio (AUD) peripheral.  <a href="#a4ddfdbb13a735158eac6316b10fe827b">More...</a><br/></td></tr>
<tr class="separator:a4ddfdbb13a735158eac6316b10fe827b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a48cc569dd4043d7d85a22e18f3e7ff14"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a48cc569dd4043d7d85a22e18f3e7ff14">XV_HdmiRx1_AudioIntrEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a48cc569dd4043d7d85a22e18f3e7ff14"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables interrupts in the HDMI RX Audio (AUD) peripheral.  <a href="#a48cc569dd4043d7d85a22e18f3e7ff14">More...</a><br/></td></tr>
<tr class="separator:a48cc569dd4043d7d85a22e18f3e7ff14"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ade46f36736274cdedf478485ef926ee8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ade46f36736274cdedf478485ef926ee8">XV_HdmiRx1_AudioIntrDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:ade46f36736274cdedf478485ef926ee8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables interrupts in the HDMI RX Audio (AUD) peripheral.  <a href="#ade46f36736274cdedf478485ef926ee8">More...</a><br/></td></tr>
<tr class="separator:ade46f36736274cdedf478485ef926ee8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3fbbc87fccf9e874431488d97de267cd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a3fbbc87fccf9e874431488d97de267cd">XV_HdmiRx1_SetAudioAcrUpdateEventEn</a>(InstancePtr)</td></tr>
<tr class="memdesc:a3fbbc87fccf9e874431488d97de267cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables ACR Update Event in the HDMI RX Audio (AUD) peripheral.  <a href="#a3fbbc87fccf9e874431488d97de267cd">More...</a><br/></td></tr>
<tr class="separator:a3fbbc87fccf9e874431488d97de267cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac008d4c353d03524eca2da14c092b1e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ac008d4c353d03524eca2da14c092b1e7">XV_HdmiRx1_ClearAudioAcrUpdateEventEn</a>(InstancePtr)</td></tr>
<tr class="memdesc:ac008d4c353d03524eca2da14c092b1e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables ACR Update Event in the HDMI RX Audio (AUD) peripheral.  <a href="#ac008d4c353d03524eca2da14c092b1e7">More...</a><br/></td></tr>
<tr class="separator:ac008d4c353d03524eca2da14c092b1e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a82a49f48613a311ebd77b7c06d774287"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a82a49f48613a311ebd77b7c06d774287">XV_HdmiRx1_LnkstaEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a82a49f48613a311ebd77b7c06d774287"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables the HDMI RX Link Status (LNKSTA) peripheral.  <a href="#a82a49f48613a311ebd77b7c06d774287">More...</a><br/></td></tr>
<tr class="separator:a82a49f48613a311ebd77b7c06d774287"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad50e1b7607576055e893d5b671ab20e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ad50e1b7607576055e893d5b671ab20e8">XV_HdmiRx1_LnkstaDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:ad50e1b7607576055e893d5b671ab20e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables the HDMI RX Link Status (LNKSTA) peripheral.  <a href="#ad50e1b7607576055e893d5b671ab20e8">More...</a><br/></td></tr>
<tr class="separator:ad50e1b7607576055e893d5b671ab20e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1f63ca19bbee2e5a8bdc3a935063a764"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a1f63ca19bbee2e5a8bdc3a935063a764">XV_HdmiRx1_LinkIntrEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a1f63ca19bbee2e5a8bdc3a935063a764"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables interrupt in the HDMI RX Link Status (LNKSTA) peripheral.  <a href="#a1f63ca19bbee2e5a8bdc3a935063a764">More...</a><br/></td></tr>
<tr class="separator:a1f63ca19bbee2e5a8bdc3a935063a764"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afaa36adac08f538ed818974141158dbd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#afaa36adac08f538ed818974141158dbd">XV_HdmiRx1_LinkIntrDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:afaa36adac08f538ed818974141158dbd"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disable interrupt in the HDMI RX Link Status (LNKSTA) peripheral.  <a href="#afaa36adac08f538ed818974141158dbd">More...</a><br/></td></tr>
<tr class="separator:afaa36adac08f538ed818974141158dbd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aba75843e30381249f64cc4fa194aa13d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#aba75843e30381249f64cc4fa194aa13d">XV_HdmiRx1_IsAudioActive</a>(InstancePtr)&#160;&#160;&#160;(InstancePtr)-&gt;Stream.Audio.Active</td></tr>
<tr class="memdesc:aba75843e30381249f64cc4fa194aa13d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro returns true is the audio stream is active else false.  <a href="#aba75843e30381249f64cc4fa194aa13d">More...</a><br/></td></tr>
<tr class="separator:aba75843e30381249f64cc4fa194aa13d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a409088a9f753dff7025b7f5779eb3206"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a409088a9f753dff7025b7f5779eb3206">XV_HdmiRx1_GetAudioChannels</a>(InstancePtr)&#160;&#160;&#160;(InstancePtr)-&gt;Stream.Audio.Channels</td></tr>
<tr class="memdesc:a409088a9f753dff7025b7f5779eb3206"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro returns the number of active audio channels.  <a href="#a409088a9f753dff7025b7f5779eb3206">More...</a><br/></td></tr>
<tr class="separator:a409088a9f753dff7025b7f5779eb3206"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8f626ebfd672df8c3b3651857fbcba55"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a8f626ebfd672df8c3b3651857fbcba55">XV_HdmiRx1_DdcHdcpClearWriteMessageBuffer</a>(InstancePtr)</td></tr>
<tr class="memdesc:a8f626ebfd672df8c3b3651857fbcba55"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro clears the HDCP write message buffer in the DDC peripheral.  <a href="#a8f626ebfd672df8c3b3651857fbcba55">More...</a><br/></td></tr>
<tr class="separator:a8f626ebfd672df8c3b3651857fbcba55"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a17d1406ed5707ecc951d48b046a28a11"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a17d1406ed5707ecc951d48b046a28a11">XV_HdmiRx1_DdcHdcpClearReadMessageBuffer</a>(InstancePtr)</td></tr>
<tr class="memdesc:a17d1406ed5707ecc951d48b046a28a11"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro clears the HDCP read message buffer in the DDC peripheral.  <a href="#a17d1406ed5707ecc951d48b046a28a11">More...</a><br/></td></tr>
<tr class="separator:a17d1406ed5707ecc951d48b046a28a11"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af65e0cebc04f0d1da21b84d1b64237ce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#af65e0cebc04f0d1da21b84d1b64237ce">XV_HdmiRx1_DynHDR_DM_Enable</a>(InstancePtr)</td></tr>
<tr class="memdesc:af65e0cebc04f0d1da21b84d1b64237ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables the data mover for Dynamic HDR.  <a href="#af65e0cebc04f0d1da21b84d1b64237ce">More...</a><br/></td></tr>
<tr class="separator:af65e0cebc04f0d1da21b84d1b64237ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a68af32f4a9ad2ed19166d4695ac73d73"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a68af32f4a9ad2ed19166d4695ac73d73">XV_HdmiRx1_DynHDR_DM_Disable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a68af32f4a9ad2ed19166d4695ac73d73"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables the data mover for Dynamic HDR.  <a href="#a68af32f4a9ad2ed19166d4695ac73d73">More...</a><br/></td></tr>
<tr class="separator:a68af32f4a9ad2ed19166d4695ac73d73"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad3d4b9503693e010add504e7f4e7979e"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiRx1_DynHdrErrType</b> </td></tr>
<tr class="separator:ad3d4b9503693e010add504e7f4e7979e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a57932e2a1e2c690514833984d086b096"><td class="memItemLeft" align="right" valign="top">typedef void(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a57932e2a1e2c690514833984d086b096">XV_HdmiRx1_Callback</a> )(void *CallbackRef)</td></tr>
<tr class="memdesc:a57932e2a1e2c690514833984d086b096"><td class="mdescLeft">&#160;</td><td class="mdescRight">Callback type for interrupt.  <a href="#a57932e2a1e2c690514833984d086b096">More...</a><br/></td></tr>
<tr class="separator:a57932e2a1e2c690514833984d086b096"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1535a73eb522f695c1ebb5982711ca8a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1535a73eb522f695c1ebb5982711ca8a"></a>
typedef void(*&#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiRx1_HdcpCallback</b> )(void *CallbackRef, int Data)</td></tr>
<tr class="separator:a1535a73eb522f695c1ebb5982711ca8a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a913144078d4fff46cf06a666faa8e8f3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_v___hdmi_rx1___config.html">XV_HdmiRx1_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a913144078d4fff46cf06a666faa8e8f3">XV_HdmiRx1_LookupConfig</a> (u16 DeviceId)</td></tr>
<tr class="memdesc:a913144078d4fff46cf06a666faa8e8f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns a reference to an <a class="el" href="struct_x_v___hdmi_rx1___config.html" title="This typedef contains configuration information for the HDMI RX core. ">XV_HdmiRx1_Config</a> structure based on the core id, <em>DeviceId</em>.  <a href="#a913144078d4fff46cf06a666faa8e8f3">More...</a><br/></td></tr>
<tr class="separator:a913144078d4fff46cf06a666faa8e8f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae8f2b92316ba8599c678aa9168d2eb24"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, <a class="el" href="struct_x_v___hdmi_rx1___config.html">XV_HdmiRx1_Config</a> *CfgPtr, UINTPTR EffectiveAddr)</td></tr>
<tr class="memdesc:ae8f2b92316ba8599c678aa9168d2eb24"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function initializes the HDMI RX core.  <a href="#ae8f2b92316ba8599c678aa9168d2eb24">More...</a><br/></td></tr>
<tr class="separator:ae8f2b92316ba8599c678aa9168d2eb24"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3a7ca7162f4a1fab75cbd46ad1006630"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a3a7ca7162f4a1fab75cbd46ad1006630">XV_HdmiRx1_SetAxiClkFreq</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, u32 ClkFreq)</td></tr>
<tr class="memdesc:a3a7ca7162f4a1fab75cbd46ad1006630"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the AXI4-Lite Clock Frequency.  <a href="#a3a7ca7162f4a1fab75cbd46ad1006630">More...</a><br/></td></tr>
<tr class="separator:a3a7ca7162f4a1fab75cbd46ad1006630"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af7fd5d8f18778311dec6be080788f6f2"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#af7fd5d8f18778311dec6be080788f6f2">XV_HdmiRx1_Clear</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:af7fd5d8f18778311dec6be080788f6f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function clears the HDMI RX variables and sets them to the defaults.  <a href="#af7fd5d8f18778311dec6be080788f6f2">More...</a><br/></td></tr>
<tr class="separator:af7fd5d8f18778311dec6be080788f6f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adca7f7b2b7849037460f1d95faa9ac7a"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#adca7f7b2b7849037460f1d95faa9ac7a">XV_HdmiRx1_SetStream</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, XVidC_PixelsPerClock Ppc, u32 Clock)</td></tr>
<tr class="memdesc:adca7f7b2b7849037460f1d95faa9ac7a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the HDMI RX stream parameters.  <a href="#adca7f7b2b7849037460f1d95faa9ac7a">More...</a><br/></td></tr>
<tr class="separator:adca7f7b2b7849037460f1d95faa9ac7a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8413882f499c0d1bef9d906564540634"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a8413882f499c0d1bef9d906564540634">XV_HdmiRx1_IsStreamUp</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a8413882f499c0d1bef9d906564540634"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function provides status of the stream.  <a href="#a8413882f499c0d1bef9d906564540634">More...</a><br/></td></tr>
<tr class="separator:a8413882f499c0d1bef9d906564540634"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4c588542caec0f1e6a2f7b7f14a85e47"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a4c588542caec0f1e6a2f7b7f14a85e47">XV_HdmiRx1_IsStreamScrambled</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a4c588542caec0f1e6a2f7b7f14a85e47"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function provides the stream scrambler status.  <a href="#a4c588542caec0f1e6a2f7b7f14a85e47">More...</a><br/></td></tr>
<tr class="separator:a4c588542caec0f1e6a2f7b7f14a85e47"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a05ec85e91c33d66e6460e24aa17d5310"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a05ec85e91c33d66e6460e24aa17d5310">XV_HdmiRx1_IsStreamConnected</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a05ec85e91c33d66e6460e24aa17d5310"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function provides the stream connected status.  <a href="#a05ec85e91c33d66e6460e24aa17d5310">More...</a><br/></td></tr>
<tr class="separator:a05ec85e91c33d66e6460e24aa17d5310"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac7552beea455de7ac51452cb284241f3"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ac7552beea455de7ac51452cb284241f3">XV_HdmiRx1_SetHpd</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, u8 SetClr)</td></tr>
<tr class="memdesc:ac7552beea455de7ac51452cb284241f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables/clear Hot-Plug-Detect.  <a href="#ac7552beea455de7ac51452cb284241f3">More...</a><br/></td></tr>
<tr class="separator:ac7552beea455de7ac51452cb284241f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a54c8f8e466187861aeeb7f1de53839c4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a54c8f8e466187861aeeb7f1de53839c4">XV_HdmiRx1_INT_VRST</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, u8 Reset)</td></tr>
<tr class="memdesc:a54c8f8e466187861aeeb7f1de53839c4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function asserts or releases the HDMI RX Internal VRST.  <a href="#a54c8f8e466187861aeeb7f1de53839c4">More...</a><br/></td></tr>
<tr class="separator:a54c8f8e466187861aeeb7f1de53839c4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a50135eae0f23d244548816d4c08893f4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a50135eae0f23d244548816d4c08893f4">XV_HdmiRx1_INT_LRST</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, u8 Reset)</td></tr>
<tr class="memdesc:a50135eae0f23d244548816d4c08893f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function asserts or releases the HDMI RX Internal LRST.  <a href="#a50135eae0f23d244548816d4c08893f4">More...</a><br/></td></tr>
<tr class="separator:a50135eae0f23d244548816d4c08893f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aba149130be3e337c3789bd0fcf3c8481"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#aba149130be3e337c3789bd0fcf3c8481">XV_HdmiRx1_EXT_VRST</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, u8 Reset)</td></tr>
<tr class="memdesc:aba149130be3e337c3789bd0fcf3c8481"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function asserts or releases the HDMI RX External VRST.  <a href="#aba149130be3e337c3789bd0fcf3c8481">More...</a><br/></td></tr>
<tr class="separator:aba149130be3e337c3789bd0fcf3c8481"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af441b03cc79286c209dbffed19fc6052"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#af441b03cc79286c209dbffed19fc6052">XV_HdmiRx1_EXT_SYSRST</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, u8 Reset)</td></tr>
<tr class="memdesc:af441b03cc79286c209dbffed19fc6052"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function asserts or releases the HDMI RX External SYSRST.  <a href="#af441b03cc79286c209dbffed19fc6052">More...</a><br/></td></tr>
<tr class="separator:af441b03cc79286c209dbffed19fc6052"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8a1adaddc73691394f2f181411fffdc7"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a8a1adaddc73691394f2f181411fffdc7">XV_HdmiRx1_SetPixelRate</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a8a1adaddc73691394f2f181411fffdc7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the pixel rate.  <a href="#a8a1adaddc73691394f2f181411fffdc7">More...</a><br/></td></tr>
<tr class="separator:a8a1adaddc73691394f2f181411fffdc7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac9cfa9c40125304ad6b85cc1c88d3b52"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ac9cfa9c40125304ad6b85cc1c88d3b52">XV_HdmiRx1_SetColorFormat</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ac9cfa9c40125304ad6b85cc1c88d3b52"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the color format.  <a href="#ac9cfa9c40125304ad6b85cc1c88d3b52">More...</a><br/></td></tr>
<tr class="separator:ac9cfa9c40125304ad6b85cc1c88d3b52"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1ba7daadc574d5f04ca24a9afc4da31b"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a1ba7daadc574d5f04ca24a9afc4da31b">XV_HdmiRx1_IsLinkStatusErrMax</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a1ba7daadc574d5f04ca24a9afc4da31b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function provides status of one of the link error counters reached the maximum value.  <a href="#a1ba7daadc574d5f04ca24a9afc4da31b">More...</a><br/></td></tr>
<tr class="separator:a1ba7daadc574d5f04ca24a9afc4da31b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a303808819a246fb16be7b208ec3b4ebf"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a303808819a246fb16be7b208ec3b4ebf">XV_HdmiRx1_ClearLinkStatus</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a303808819a246fb16be7b208ec3b4ebf"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function clears the link error counters.  <a href="#a303808819a246fb16be7b208ec3b4ebf">More...</a><br/></td></tr>
<tr class="separator:a303808819a246fb16be7b208ec3b4ebf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0cc1226093e566991849c308ebf9343a"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a0cc1226093e566991849c308ebf9343a">XV_HdmiRx1_GetLinkStatus</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, u8 Type)</td></tr>
<tr class="memdesc:a0cc1226093e566991849c308ebf9343a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function provides status of the HDMI RX core Link Status peripheral.  <a href="#a0cc1226093e566991849c308ebf9343a">More...</a><br/></td></tr>
<tr class="separator:a0cc1226093e566991849c308ebf9343a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad6862d6b700903b0fde41c14f49c56ef"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ad6862d6b700903b0fde41c14f49c56ef">XV_HdmiRx1_GetAcrCts</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ad6862d6b700903b0fde41c14f49c56ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function provides audio clock regenerating CTS (Cycle-Time Stamp) value at the HDMI sink device.  <a href="#ad6862d6b700903b0fde41c14f49c56ef">More...</a><br/></td></tr>
<tr class="separator:ad6862d6b700903b0fde41c14f49c56ef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad372b661989dfb070a6931b88aadad86"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ad372b661989dfb070a6931b88aadad86">XV_HdmiRx1_GetAcrN</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ad372b661989dfb070a6931b88aadad86"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function provides audio clock regenerating factor N value.  <a href="#ad372b661989dfb070a6931b88aadad86">More...</a><br/></td></tr>
<tr class="separator:ad372b661989dfb070a6931b88aadad86"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7de516253c3c6e3deb0e6141be953e35"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a7de516253c3c6e3deb0e6141be953e35">XV_HdmiRx1_DdcLoadEdid</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, u8 *Data, u16 Length)</td></tr>
<tr class="memdesc:a7de516253c3c6e3deb0e6141be953e35"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function loads the EDID data into the DDC slave.  <a href="#a7de516253c3c6e3deb0e6141be953e35">More...</a><br/></td></tr>
<tr class="separator:a7de516253c3c6e3deb0e6141be953e35"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1b06bffa2fe0f7ec948c2df2c9e7bd18"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a1b06bffa2fe0f7ec948c2df2c9e7bd18">XV_HdmiRx1_DdcHdcpSetAddress</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, u32 Addr)</td></tr>
<tr class="memdesc:a1b06bffa2fe0f7ec948c2df2c9e7bd18"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the HDCP address in the DDC peripheral.  <a href="#a1b06bffa2fe0f7ec948c2df2c9e7bd18">More...</a><br/></td></tr>
<tr class="separator:a1b06bffa2fe0f7ec948c2df2c9e7bd18"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acfd29595f76ba68f48eb651e8c97e1b8"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#acfd29595f76ba68f48eb651e8c97e1b8">XV_HdmiRx1_DdcHdcpWriteData</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, u32 Data)</td></tr>
<tr class="memdesc:acfd29595f76ba68f48eb651e8c97e1b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function writes HDCP data in the DDC peripheral.  <a href="#acfd29595f76ba68f48eb651e8c97e1b8">More...</a><br/></td></tr>
<tr class="separator:acfd29595f76ba68f48eb651e8c97e1b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a00e93fe81aff1008cf3302164029d8a2"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a00e93fe81aff1008cf3302164029d8a2">XV_HdmiRx1_DdcHdcpReadData</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a00e93fe81aff1008cf3302164029d8a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function reads HDCP data from the DDC peripheral.  <a href="#a00e93fe81aff1008cf3302164029d8a2">More...</a><br/></td></tr>
<tr class="separator:a00e93fe81aff1008cf3302164029d8a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a73ddb323bea902304e9078c943ffab9d"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a73ddb323bea902304e9078c943ffab9d">XV_HdmiRx1_DdcGetHdcpWriteMessageBufferWords</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a73ddb323bea902304e9078c943ffab9d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the number of bytes of the HDCP 2.2 write buffer in the DDC slave.  <a href="#a73ddb323bea902304e9078c943ffab9d">More...</a><br/></td></tr>
<tr class="separator:a73ddb323bea902304e9078c943ffab9d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a68b8778ca3dd3b9be8cfe9315837bed7"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a68b8778ca3dd3b9be8cfe9315837bed7">XV_HdmiRx1_DdcIsHdcpWriteMessageBufferEmpty</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a68b8778ca3dd3b9be8cfe9315837bed7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the status of the HDCP 2.2 write buffer in the DDC slave.  <a href="#a68b8778ca3dd3b9be8cfe9315837bed7">More...</a><br/></td></tr>
<tr class="separator:a68b8778ca3dd3b9be8cfe9315837bed7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a408d0c1659d09261cff536cf6226720c"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a408d0c1659d09261cff536cf6226720c">XV_HdmiRx1_DdcGetHdcpReadMessageBufferWords</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a408d0c1659d09261cff536cf6226720c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the number of bytes of the HDCP 2.2 read buffer in the DDC slave.  <a href="#a408d0c1659d09261cff536cf6226720c">More...</a><br/></td></tr>
<tr class="separator:a408d0c1659d09261cff536cf6226720c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a533b81d0c208429a0d535d72d183d988"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a533b81d0c208429a0d535d72d183d988">XV_HdmiRx1_DdcIsHdcpReadMessageBufferEmpty</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a533b81d0c208429a0d535d72d183d988"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the status of the HDCP 2.2 read message buffer in the DDC slave.  <a href="#a533b81d0c208429a0d535d72d183d988">More...</a><br/></td></tr>
<tr class="separator:a533b81d0c208429a0d535d72d183d988"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6c66ee7dbad42980fb2297404ee4fa7a"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a6c66ee7dbad42980fb2297404ee4fa7a">XV_HdmiRx1_GetTmdsClockRatio</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a6c66ee7dbad42980fb2297404ee4fa7a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the SCDC TMDS clock ratio bit.  <a href="#a6c66ee7dbad42980fb2297404ee4fa7a">More...</a><br/></td></tr>
<tr class="separator:a6c66ee7dbad42980fb2297404ee4fa7a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab77058d12d39a6cae1920402ad231de8"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ab77058d12d39a6cae1920402ad231de8">XV_HdmiRx1_GetAviVic</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ab77058d12d39a6cae1920402ad231de8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the AVI VIC (captured by the AUX peripheral)  <a href="#ab77058d12d39a6cae1920402ad231de8">More...</a><br/></td></tr>
<tr class="separator:ab77058d12d39a6cae1920402ad231de8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad4f280e6064c750dcc09cdd3bdcaa408"><td class="memItemLeft" align="right" valign="top">XVidC_ColorFormat&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ad4f280e6064c750dcc09cdd3bdcaa408">XV_HdmiRx1_GetAviColorSpace</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ad4f280e6064c750dcc09cdd3bdcaa408"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the AVI colorspace (captured by the AUX peripheral)  <a href="#ad4f280e6064c750dcc09cdd3bdcaa408">More...</a><br/></td></tr>
<tr class="separator:ad4f280e6064c750dcc09cdd3bdcaa408"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4c6e4ca31c0b284eaa58924dd42d1d13"><td class="memItemLeft" align="right" valign="top">XVidC_ColorDepth&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a4c6e4ca31c0b284eaa58924dd42d1d13">XV_HdmiRx1_GetGcpColorDepth</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a4c6e4ca31c0b284eaa58924dd42d1d13"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the GCP color depth (captured by the AUX peripheral)  <a href="#a4c6e4ca31c0b284eaa58924dd42d1d13">More...</a><br/></td></tr>
<tr class="separator:a4c6e4ca31c0b284eaa58924dd42d1d13"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a77f3a5723008c8604137960daa6174bd"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a77f3a5723008c8604137960daa6174bd">XV_HdmiRx1_GetVideoProperties</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a77f3a5723008c8604137960daa6174bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function reads the video properties from the aux peripheral.  <a href="#a77f3a5723008c8604137960daa6174bd">More...</a><br/></td></tr>
<tr class="separator:a77f3a5723008c8604137960daa6174bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aeb4be084a07a96cd89d3f4386fbadae2"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#aeb4be084a07a96cd89d3f4386fbadae2">XV_HdmiRx1_GetVideoTiming</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:aeb4be084a07a96cd89d3f4386fbadae2"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function reads the video timing from the VTD peripheral.  <a href="#aeb4be084a07a96cd89d3f4386fbadae2">More...</a><br/></td></tr>
<tr class="separator:aeb4be084a07a96cd89d3f4386fbadae2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a324586d14f5578cd7e037650380c0dc4"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a324586d14f5578cd7e037650380c0dc4">XV_HdmiRx1_Divide</a> (u32 Dividend, u32 Divisor)</td></tr>
<tr class="memdesc:a324586d14f5578cd7e037650380c0dc4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function calculates the divider for the frame calculation.  <a href="#a324586d14f5578cd7e037650380c0dc4">More...</a><br/></td></tr>
<tr class="separator:a324586d14f5578cd7e037650380c0dc4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abd15bdeaefdc3438e5b1ddeb17670efa"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#abd15bdeaefdc3438e5b1ddeb17670efa">XV_HdmiRx1_SetPixelClk</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:abd15bdeaefdc3438e5b1ddeb17670efa"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the PixelClk based on the current ColorDepth, RefClk and ColorFormatId.  <a href="#abd15bdeaefdc3438e5b1ddeb17670efa">More...</a><br/></td></tr>
<tr class="separator:abd15bdeaefdc3438e5b1ddeb17670efa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a331430d0474344d993eb016fca535e65"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a331430d0474344d993eb016fca535e65">XV_HdmiRx1_Start</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a331430d0474344d993eb016fca535e65"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function starts the HDMI RX core.  <a href="#a331430d0474344d993eb016fca535e65">More...</a><br/></td></tr>
<tr class="separator:a331430d0474344d993eb016fca535e65"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aacd8eb82c28cab7d1e72d51f7e4923b8"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#aacd8eb82c28cab7d1e72d51f7e4923b8">XV_HdmiRx1_Stop</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:aacd8eb82c28cab7d1e72d51f7e4923b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function stops the HDMI RX core.  <a href="#aacd8eb82c28cab7d1e72d51f7e4923b8">More...</a><br/></td></tr>
<tr class="separator:aacd8eb82c28cab7d1e72d51f7e4923b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8fde9d6293c66dde0cb3d18dfbf2375a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a8fde9d6293c66dde0cb3d18dfbf2375a">XV_HdmiRx1_UpdateEdFlags</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a8fde9d6293c66dde0cb3d18dfbf2375a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function checks if RX's CED or RSED counters are incrementing at the rate of 4 or higher per second or if they first hit the maximum value (0x7FFF) then set the CED_Update or RSED_Update SCDC flags if true.  <a href="#a8fde9d6293c66dde0cb3d18dfbf2375a">More...</a><br/></td></tr>
<tr class="separator:a8fde9d6293c66dde0cb3d18dfbf2375a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af10ef171597554725eb963e6ee83278b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#af10ef171597554725eb963e6ee83278b">XV_HdmiRx1_TmrStartMs</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, u32 Milliseconds, u8 TimerSelect)</td></tr>
<tr class="memdesc:af10ef171597554725eb963e6ee83278b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the timer of RX Core.  <a href="#af10ef171597554725eb963e6ee83278b">More...</a><br/></td></tr>
<tr class="separator:af10ef171597554725eb963e6ee83278b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab09051531748d89ef3d9af63d542c07d"><td class="memItemLeft" align="right" valign="top">XVidC_VideoMode&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ab09051531748d89ef3d9af63d542c07d">XV_HdmiRx1_LookupVmId</a> (u8 Vic)</td></tr>
<tr class="memdesc:ab09051531748d89ef3d9af63d542c07d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function searches for the video mode based on the vic.  <a href="#ab09051531748d89ef3d9af63d542c07d">More...</a><br/></td></tr>
<tr class="separator:ab09051531748d89ef3d9af63d542c07d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1900b5ae3eed522d1c983b3dfb169ac3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1900b5ae3eed522d1c983b3dfb169ac3"></a>
void&#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiRx1_ParseSrcProdDescInfoframe</b> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="separator:a1900b5ae3eed522d1c983b3dfb169ac3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abd60d1348aae2020ed7ae9ee0e3e47a0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abd60d1348aae2020ed7ae9ee0e3e47a0"></a>
void&#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiRx1_ParseVideoTimingExtMetaIF</b> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="separator:abd60d1348aae2020ed7ae9ee0e3e47a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8b8df1df4274fd34afc6ad600c4d1605"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a8b8df1df4274fd34afc6ad600c4d1605">XV_HdmiRx1_FrlModeEnable</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, u8 LtpThreshold, XV_HdmiRx1_FrlLtp DefaultLtp, u8 FfeSuppFlag)</td></tr>
<tr class="memdesc:a8b8df1df4274fd34afc6ad600c4d1605"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables the FRL mode.  <a href="#a8b8df1df4274fd34afc6ad600c4d1605">More...</a><br/></td></tr>
<tr class="separator:a8b8df1df4274fd34afc6ad600c4d1605"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adaa4205184958f79b8aa3d2e39b97661"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#adaa4205184958f79b8aa3d2e39b97661">XV_HdmiRx1_ExecFrlState</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:adaa4205184958f79b8aa3d2e39b97661"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function executes the different of states of FRL.  <a href="#adaa4205184958f79b8aa3d2e39b97661">More...</a><br/></td></tr>
<tr class="separator:adaa4205184958f79b8aa3d2e39b97661"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af9ac94749a5d49d68879dda13618a3fd"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#af9ac94749a5d49d68879dda13618a3fd">XV_HdmiRx1_GetPatternsMatchStatus</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:af9ac94749a5d49d68879dda13618a3fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the status of the patterns matched lanes.  <a href="#af9ac94749a5d49d68879dda13618a3fd">More...</a><br/></td></tr>
<tr class="separator:af9ac94749a5d49d68879dda13618a3fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adebf854f66fb92c37366faab549dd4a8"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#adebf854f66fb92c37366faab549dd4a8">XV_HdmiRx1_PhyResetPoll</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:adebf854f66fb92c37366faab549dd4a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function polls the pattern matching status and decide if the Phy needs to be reset or not.  <a href="#adebf854f66fb92c37366faab549dd4a8">More...</a><br/></td></tr>
<tr class="separator:adebf854f66fb92c37366faab549dd4a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a07be19e39e2a3e90ea9ac937f6adfc58"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a07be19e39e2a3e90ea9ac937f6adfc58">XV_HdmiRx1_FrlLinkRetrain</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, u8 LtpThreshold, XV_HdmiRx1_FrlLtp DefaultLtp)</td></tr>
<tr class="memdesc:a07be19e39e2a3e90ea9ac937f6adfc58"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function initiates FRL rate dropping procedure.  <a href="#a07be19e39e2a3e90ea9ac937f6adfc58">More...</a><br/></td></tr>
<tr class="separator:a07be19e39e2a3e90ea9ac937f6adfc58"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a04b941fdfc281d7d81665d47ac32f1d2"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a04b941fdfc281d7d81665d47ac32f1d2">XV_HdmiRx1_FrlReset</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, u8 Reset)</td></tr>
<tr class="memdesc:a04b941fdfc281d7d81665d47ac32f1d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function resets the FRL peripheral.  <a href="#a04b941fdfc281d7d81665d47ac32f1d2">More...</a><br/></td></tr>
<tr class="separator:a04b941fdfc281d7d81665d47ac32f1d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad8f801766bca274f8235adde45ddc085"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ad8f801766bca274f8235adde45ddc085">XV_HdmiRx1_ConfigFrlLtpDetection</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ad8f801766bca274f8235adde45ddc085"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function configures the link training pattern to be detected.  <a href="#ad8f801766bca274f8235adde45ddc085">More...</a><br/></td></tr>
<tr class="separator:ad8f801766bca274f8235adde45ddc085"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adf3222be232d5b0eaabeb5fbba4258fa"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#adf3222be232d5b0eaabeb5fbba4258fa">XV_HdmiRx1_SetFrlLtpDetection</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, u8 Lane, XV_HdmiRx1_FrlLtpType Ltp)</td></tr>
<tr class="memdesc:adf3222be232d5b0eaabeb5fbba4258fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the link training pattern to be detected for the selected lane.  <a href="#adf3222be232d5b0eaabeb5fbba4258fa">More...</a><br/></td></tr>
<tr class="separator:adf3222be232d5b0eaabeb5fbba4258fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6010db11abd7d7a7b935d20b693c5b7a"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a6010db11abd7d7a7b935d20b693c5b7a">XV_HdmiRx1_GetFrlLtpDetection</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, u8 Lane)</td></tr>
<tr class="memdesc:a6010db11abd7d7a7b935d20b693c5b7a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the link training pattern to be detected for the selected lane.  <a href="#a6010db11abd7d7a7b935d20b693c5b7a">More...</a><br/></td></tr>
<tr class="separator:a6010db11abd7d7a7b935d20b693c5b7a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0544f5226d2072e3a594677139f54d70"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a0544f5226d2072e3a594677139f54d70">XV_HdmiRx1_ResetFrlLtpDetection</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a0544f5226d2072e3a594677139f54d70"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function reset the link training pattern for the specified lane.  <a href="#a0544f5226d2072e3a594677139f54d70">More...</a><br/></td></tr>
<tr class="separator:a0544f5226d2072e3a594677139f54d70"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae387ae2d8723aa7ae9367694b70ac03f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ae387ae2d8723aa7ae9367694b70ac03f">XV_HdmiRx1_FrlLtpDetectionEnable</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ae387ae2d8723aa7ae9367694b70ac03f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables the LTP detection module.  <a href="#ae387ae2d8723aa7ae9367694b70ac03f">More...</a><br/></td></tr>
<tr class="separator:ae387ae2d8723aa7ae9367694b70ac03f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a82e80b12dafcd1984f11cbddbbd68551"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a82e80b12dafcd1984f11cbddbbd68551">XV_HdmiRx1_FrlLtpDetectionDisable</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a82e80b12dafcd1984f11cbddbbd68551"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function disables the LTP detection module.  <a href="#a82e80b12dafcd1984f11cbddbbd68551">More...</a><br/></td></tr>
<tr class="separator:a82e80b12dafcd1984f11cbddbbd68551"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a095b12f733544b877279ea062c592a7d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a095b12f733544b877279ea062c592a7d">XV_HdmiRx1_SetFrlLtpThreshold</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, u8 Threshold)</td></tr>
<tr class="memdesc:a095b12f733544b877279ea062c592a7d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the number of times the full link training patterns need to be matched before it is considered as a lock.  <a href="#a095b12f733544b877279ea062c592a7d">More...</a><br/></td></tr>
<tr class="separator:a095b12f733544b877279ea062c592a7d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a580b1f726297a49e552e2e90aa7a80f4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a580b1f726297a49e552e2e90aa7a80f4">XV_HdmiRx1_RetrieveFrlRateLanes</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a580b1f726297a49e552e2e90aa7a80f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function updates the software's FRL Rate and FRL Lanes by reading and decoding the information from the RX core.  <a href="#a580b1f726297a49e552e2e90aa7a80f4">More...</a><br/></td></tr>
<tr class="separator:a580b1f726297a49e552e2e90aa7a80f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4806363b327ac1b624d0b470ab46c142"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a4806363b327ac1b624d0b470ab46c142">XV_HdmiRx1_SetFrlRateWrEvent_En</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a4806363b327ac1b624d0b470ab46c142"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the FRL rate write enable Event.  <a href="#a4806363b327ac1b624d0b470ab46c142">More...</a><br/></td></tr>
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<tr class="memitem:ab17e4f96ebbe6785b411233165de859a"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ab17e4f96ebbe6785b411233165de859a">XV_HdmiRx1_FrlDdcWriteField</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, XV_HdmiRx1_FrlScdcFieldType Field, u8 Value)</td></tr>
<tr class="memdesc:ab17e4f96ebbe6785b411233165de859a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function writes the specified FRL SCDC Field.  <a href="#ab17e4f96ebbe6785b411233165de859a">More...</a><br/></td></tr>
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<tr class="memitem:a38c0efa82d512c42b07775e36f919bb2"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a38c0efa82d512c42b07775e36f919bb2">XV_HdmiRx1_FrlDdcReadField</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, XV_HdmiRx1_FrlScdcFieldType Field)</td></tr>
<tr class="memdesc:a38c0efa82d512c42b07775e36f919bb2"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function reads the specified FRL SCDC Field.  <a href="#a38c0efa82d512c42b07775e36f919bb2">More...</a><br/></td></tr>
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void&#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiRx1_SetFrlFltNoTimeout</b> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
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<tr class="memitem:a68caa6d57e7410b73c74d55225d99ba8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a68caa6d57e7410b73c74d55225d99ba8"></a>
void&#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiRx1_ClearFrlFltNoTimeout</b> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
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<tr class="memitem:aa8fec3226e7abab9b6a14251bd8705ba"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#aa8fec3226e7abab9b6a14251bd8705ba">XV_HdmiRx1_SetFrl10MicroSecondsTimer</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:aa8fec3226e7abab9b6a14251bd8705ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the timer of RX Core's FRL peripheral for 10 Microseconds.  <a href="#aa8fec3226e7abab9b6a14251bd8705ba">More...</a><br/></td></tr>
<tr class="separator:aa8fec3226e7abab9b6a14251bd8705ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afd29a2caefd6060c3546e3debe17f03b"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#afd29a2caefd6060c3546e3debe17f03b">XV_HdmiRx1_GetFrlTotalPixRatio</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:afd29a2caefd6060c3546e3debe17f03b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function provides FRL Ratio (Total Pixel)  <a href="#afd29a2caefd6060c3546e3debe17f03b">More...</a><br/></td></tr>
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<tr class="memitem:abcaa2a7e3e0a31a5d19b99179e70c636"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#abcaa2a7e3e0a31a5d19b99179e70c636">XV_HdmiRx1_GetFrlActivePixRatio</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:abcaa2a7e3e0a31a5d19b99179e70c636"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function provides FRL Ratio (Active Pixel)  <a href="#abcaa2a7e3e0a31a5d19b99179e70c636">More...</a><br/></td></tr>
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<tr class="memitem:ab503fffe5f05b062de6b262bcc65fb55"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab503fffe5f05b062de6b262bcc65fb55"></a>
void&#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiRx1_RestartFrlLt</b> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
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<tr class="memitem:a4019c04b263a697ffa8a761cdb3a236a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4019c04b263a697ffa8a761cdb3a236a"></a>
void&#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiRx1_FrlFltUpdate</b> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, u8 Flag)</td></tr>
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<tr class="memitem:ae0a56a031d91c3f249937963dfce4c32"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ae0a56a031d91c3f249937963dfce4c32">XV_HdmiRx1_Info</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ae0a56a031d91c3f249937963dfce4c32"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function prints stream and timing information on STDIO/UART console.  <a href="#ae0a56a031d91c3f249937963dfce4c32">More...</a><br/></td></tr>
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<tr class="memitem:a13af54cb5eac5be1f950b9f9ee4773a7"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a13af54cb5eac5be1f950b9f9ee4773a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function prints debug information on STDIO/UART console.  <a href="#a13af54cb5eac5be1f950b9f9ee4773a7">More...</a><br/></td></tr>
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<tr class="memitem:a8c36e5246bc11755fd3041843a4c0183"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a8c36e5246bc11755fd3041843a4c0183">XV_HdmiRx1_RegisterDebug</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a8c36e5246bc11755fd3041843a4c0183"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function prints out HDMI RX register.  <a href="#a8c36e5246bc11755fd3041843a4c0183">More...</a><br/></td></tr>
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<tr class="memitem:ae9e628e19196bcade3dd720dc86db3a6"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#ae9e628e19196bcade3dd720dc86db3a6">XV_HdmiRx1_DdcRegDump</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ae9e628e19196bcade3dd720dc86db3a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function prints out RX's SCDC registers and values on STDIO/UART.  <a href="#ae9e628e19196bcade3dd720dc86db3a6">More...</a><br/></td></tr>
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<tr class="memitem:abaa46cfd50c028ac5b941638dceb7bb7"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#abaa46cfd50c028ac5b941638dceb7bb7">XV_HdmiRx1_SelfTest</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:abaa46cfd50c028ac5b941638dceb7bb7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function reads ID of PIO peripheral.  <a href="#abaa46cfd50c028ac5b941638dceb7bb7">More...</a><br/></td></tr>
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<tr class="memitem:aa63dbee16a4d7face7e6d6aa49bef361"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#aa63dbee16a4d7face7e6d6aa49bef361">XV_HdmiRx1_IntrHandler</a> (void *InstancePtr)</td></tr>
<tr class="memdesc:aa63dbee16a4d7face7e6d6aa49bef361"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is the interrupt handler for the HDMI RX driver.  <a href="#aa63dbee16a4d7face7e6d6aa49bef361">More...</a><br/></td></tr>
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<tr class="memitem:a7039dd1c40555eb136d7fcddda44d7b0"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a7039dd1c40555eb136d7fcddda44d7b0">XV_HdmiRx1_SetCallback</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942">XV_HdmiRx1_HandlerType</a> HandlerType, void *CallbackFunc, void *CallbackRef)</td></tr>
<tr class="memdesc:a7039dd1c40555eb136d7fcddda44d7b0"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function installs an asynchronous callback function for the given HandlerType:  <a href="#a7039dd1c40555eb136d7fcddda44d7b0">More...</a><br/></td></tr>
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<tr class="memitem:a256ae5d3354dc6dfc7f0ee9823054fd4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a256ae5d3354dc6dfc7f0ee9823054fd4"></a>
XV_HdmiC_VideoTimingExtMeta *&#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiRx1_GetVidTimingExtMeta</b> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
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<tr class="memitem:a190fc318896fa447dea0985e8a5aeda0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a190fc318896fa447dea0985e8a5aeda0"></a>
XV_HdmiC_SrcProdDescIF *&#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiRx1_GetSrcProdDescIF</b> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
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<tr class="memitem:a34282e19418aecffbb5c59ee9a217339"><td class="memItemLeft" align="right" valign="top">XV_HdmiC_VrrInfoframeType&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#a34282e19418aecffbb5c59ee9a217339">XV_HdmiRx1_GetVrrIfType</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a34282e19418aecffbb5c59ee9a217339"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns VRR infoframe type.  <a href="#a34282e19418aecffbb5c59ee9a217339">More...</a><br/></td></tr>
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<tr class="memitem:aad257ad1f1f6c43a90f3bb06a485da36"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#aad257ad1f1f6c43a90f3bb06a485da36">XV_HdmiRx1_SetVrrIfType</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, XV_HdmiC_VrrInfoframeType Type)</td></tr>
<tr class="memdesc:aad257ad1f1f6c43a90f3bb06a485da36"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function Sets VRR infoframe type.  <a href="#aad257ad1f1f6c43a90f3bb06a485da36">More...</a><br/></td></tr>
<tr class="separator:aad257ad1f1f6c43a90f3bb06a485da36"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aadab16501ebe113f3881aa7c7d2091f1"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#aadab16501ebe113f3881aa7c7d2091f1">XV_HdmiRx1_DynHDR_SetAddr</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, u64 Addr)</td></tr>
<tr class="memdesc:aadab16501ebe113f3881aa7c7d2091f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the Dynamic HDR buffer address.  <a href="#aadab16501ebe113f3881aa7c7d2091f1">More...</a><br/></td></tr>
<tr class="separator:aadab16501ebe113f3881aa7c7d2091f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa8d5e2d39022661864bdf89e0fca6b3d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1_8h.html#aa8d5e2d39022661864bdf89e0fca6b3d">XV_HdmiRx1_DynHDR_GetInfo</a> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr, <a class="el" href="struct_x_v___hdmi_rx1___dyn_h_d_r___info.html">XV_HdmiRx1_DynHDR_Info</a> *RxDynInfoPtr)</td></tr>
<tr class="memdesc:aa8d5e2d39022661864bdf89e0fca6b3d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the Dynamic HDR packet type, length, whether graphics overlay and errors if any.  <a href="#aa8d5e2d39022661864bdf89e0fca6b3d">More...</a><br/></td></tr>
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u32&#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiRx1_DSC_IsEnableStream</b> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
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<tr class="memitem:a663b65d386f0ebc0236a130bb471e444"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a663b65d386f0ebc0236a130bb471e444"></a>
int&#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiRx1_DSC_SetDecodeFail</b> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
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<tr class="memitem:a8e9ad663068e767a0e47d04fcf330967"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8e9ad663068e767a0e47d04fcf330967"></a>
int&#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiRx1_DSC_SetDscFrlMax</b> (<a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *InstancePtr)</td></tr>
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</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a4ddfdbb13a735158eac6316b10fe827b"></a>
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          <td class="memname">#define XV_HdmiRx1_AudioDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
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</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ac3b08fa2ae41be9a6904419b439d79f3">XV_HDMIRX1_AUD_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a025c0ac63f58c4d1b532ce2c49cc168d">XV_HDMIRX1_AUD_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a025c0ac63f58c4d1b532ce2c49cc168d"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a025c0ac63f58c4d1b532ce2c49cc168d">XV_HDMIRX1_AUD_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_AUD_CTRL_RUN_MASK</div><div class="ttdoc">AUD Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:426</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ac3b08fa2ae41be9a6904419b439d79f3"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ac3b08fa2ae41be9a6904419b439d79f3">XV_HDMIRX1_AUD_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_AUD_CTRL_CLR_OFFSET</div><div class="ttdoc">AUD Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:420</div></div>
</div><!-- fragment -->
<p>This macro disables the HDMI RX Audio (AUD) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a4ddfdbb13a735158eac6316b10fe827b" title="This macro disables the HDMI RX Audio (AUD) peripheral. ">XV_HdmiRx1_AudioDisable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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          <td class="memname">#define XV_HdmiRx1_AudioEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a6144291d33bdfd02d9077042fb6a5f0d">XV_HDMIRX1_AUD_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a025c0ac63f58c4d1b532ce2c49cc168d">XV_HDMIRX1_AUD_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a025c0ac63f58c4d1b532ce2c49cc168d"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a025c0ac63f58c4d1b532ce2c49cc168d">XV_HDMIRX1_AUD_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_AUD_CTRL_RUN_MASK</div><div class="ttdoc">AUD Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:426</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a6144291d33bdfd02d9077042fb6a5f0d"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a6144291d33bdfd02d9077042fb6a5f0d">XV_HDMIRX1_AUD_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_AUD_CTRL_SET_OFFSET</div><div class="ttdoc">AUD Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:419</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
</div><!-- fragment -->
<p>This macro enables the HDMI RX Audio (AUD) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a3994fbc415670b527fa40e4b634c9f49" title="This macro enables the HDMI RX Audio (AUD) peripheral. ">XV_HdmiRx1_AudioEnable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_AudioIntrDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ac3b08fa2ae41be9a6904419b439d79f3">XV_HDMIRX1_AUD_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ad9cead30e8cec1e057a5670382f85aac">XV_HDMIRX1_AUD_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ac3b08fa2ae41be9a6904419b439d79f3"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ac3b08fa2ae41be9a6904419b439d79f3">XV_HDMIRX1_AUD_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_AUD_CTRL_CLR_OFFSET</div><div class="ttdoc">AUD Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:420</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ad9cead30e8cec1e057a5670382f85aac"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ad9cead30e8cec1e057a5670382f85aac">XV_HDMIRX1_AUD_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_AUD_CTRL_IE_MASK</div><div class="ttdoc">AUD Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:427</div></div>
</div><!-- fragment -->
<p>This macro disables interrupts in the HDMI RX Audio (AUD) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#ade46f36736274cdedf478485ef926ee8" title="This macro disables interrupts in the HDMI RX Audio (AUD) peripheral. ">XV_HdmiRx1_AudioIntrDisable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="a48cc569dd4043d7d85a22e18f3e7ff14"></a>
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          <td class="memname">#define XV_HdmiRx1_AudioIntrEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a6144291d33bdfd02d9077042fb6a5f0d">XV_HDMIRX1_AUD_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ad9cead30e8cec1e057a5670382f85aac">XV_HDMIRX1_AUD_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a6144291d33bdfd02d9077042fb6a5f0d"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a6144291d33bdfd02d9077042fb6a5f0d">XV_HDMIRX1_AUD_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_AUD_CTRL_SET_OFFSET</div><div class="ttdoc">AUD Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:419</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ad9cead30e8cec1e057a5670382f85aac"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ad9cead30e8cec1e057a5670382f85aac">XV_HDMIRX1_AUD_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_AUD_CTRL_IE_MASK</div><div class="ttdoc">AUD Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:427</div></div>
</div><!-- fragment -->
<p>This macro enables interrupts in the HDMI RX Audio (AUD) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a48cc569dd4043d7d85a22e18f3e7ff14" title="This macro enables interrupts in the HDMI RX Audio (AUD) peripheral. ">XV_HdmiRx1_AudioIntrEnable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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          <td class="memname">#define XV_HdmiRx1_AuxDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#add9bba9228d3f408182b26777c21aa2b">XV_HDMIRX1_AUX_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ac798bb32a30b17ca65d0f3371172963c">XV_HDMIRX1_AUX_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ac798bb32a30b17ca65d0f3371172963c"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ac798bb32a30b17ca65d0f3371172963c">XV_HDMIRX1_AUX_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_AUX_CTRL_RUN_MASK</div><div class="ttdoc">AUX Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:324</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_add9bba9228d3f408182b26777c21aa2b"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#add9bba9228d3f408182b26777c21aa2b">XV_HDMIRX1_AUX_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_AUX_CTRL_CLR_OFFSET</div><div class="ttdoc">AUX Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:312</div></div>
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<p>This macro disables the HDMI RX Auxiliary (AUX) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#ab7b551cd29147914edb614a75ad72106" title="This macro disables the HDMI RX Auxiliary (AUX) peripheral. ">XV_HdmiRx1_AuxDisable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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          <td class="memname">#define XV_HdmiRx1_AuxEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ac751b5b5be3fe003fe43f056f292bbf0">XV_HDMIRX1_AUX_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ac798bb32a30b17ca65d0f3371172963c">XV_HDMIRX1_AUX_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ac798bb32a30b17ca65d0f3371172963c"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ac798bb32a30b17ca65d0f3371172963c">XV_HDMIRX1_AUX_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_AUX_CTRL_RUN_MASK</div><div class="ttdoc">AUX Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:324</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ac751b5b5be3fe003fe43f056f292bbf0"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ac751b5b5be3fe003fe43f056f292bbf0">XV_HDMIRX1_AUX_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_AUX_CTRL_SET_OFFSET</div><div class="ttdoc">AUX Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:311</div></div>
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<p>This macro enables the HDMI RX Auxiliary (AUX) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a2c5da76a0a84df38663bea3d958bbb40" title="This macro enables the HDMI RX Auxiliary (AUX) peripheral. ">XV_HdmiRx1_AuxEnable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_AuxFSyncVrrChEvtDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#add9bba9228d3f408182b26777c21aa2b">XV_HDMIRX1_AUX_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a0b6e46c9f463bf6c605f76ccc61c9f32">XV_HDMIRX1_AUX_CTRL_FSYNC_VRR_CH_EVT_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a0b6e46c9f463bf6c605f76ccc61c9f32"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a0b6e46c9f463bf6c605f76ccc61c9f32">XV_HDMIRX1_AUX_CTRL_FSYNC_VRR_CH_EVT_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_AUX_CTRL_FSYNC_VRR_CH_EVT_MASK</div><div class="ttdoc">AUX Control FSync/VRR change event enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:326</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_add9bba9228d3f408182b26777c21aa2b"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#add9bba9228d3f408182b26777c21aa2b">XV_HDMIRX1_AUX_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_AUX_CTRL_CLR_OFFSET</div><div class="ttdoc">AUX Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:312</div></div>
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<p>This macro disables FSync/VRR event interrupt in the HDMI RX Auxiliary (AUX) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a33ea1831b4176642737b0ab57a821130" title="This macro disables FSync/VRR event interrupt in the HDMI RX Auxiliary (AUX) peripheral. ">XV_HdmiRx1_AuxFSyncVrrChEvtDisable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="a167821ef9d8c222d4d8c1bc194e1d42b"></a>
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          <td class="memname">#define XV_HdmiRx1_AuxFSyncVrrChEvtEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ac751b5b5be3fe003fe43f056f292bbf0">XV_HDMIRX1_AUX_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a0b6e46c9f463bf6c605f76ccc61c9f32">XV_HDMIRX1_AUX_CTRL_FSYNC_VRR_CH_EVT_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a0b6e46c9f463bf6c605f76ccc61c9f32"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a0b6e46c9f463bf6c605f76ccc61c9f32">XV_HDMIRX1_AUX_CTRL_FSYNC_VRR_CH_EVT_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_AUX_CTRL_FSYNC_VRR_CH_EVT_MASK</div><div class="ttdoc">AUX Control FSync/VRR change event enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:326</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ac751b5b5be3fe003fe43f056f292bbf0"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ac751b5b5be3fe003fe43f056f292bbf0">XV_HDMIRX1_AUX_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_AUX_CTRL_SET_OFFSET</div><div class="ttdoc">AUX Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:311</div></div>
</div><!-- fragment -->
<p>This macro enables FSync/VRR event interrupt in the HDMI RX Auxiliary (AUX) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a167821ef9d8c222d4d8c1bc194e1d42b" title="This macro enables FSync/VRR event interrupt in the HDMI RX Auxiliary (AUX) peripheral. ">XV_HdmiRx1_AuxFSyncVrrChEvtEnable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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<a class="anchor" id="a1795c1a58886dfef4dff8d48d83781f5"></a>
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          <td class="memname">#define XV_HdmiRx1_AuxIntrDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#add9bba9228d3f408182b26777c21aa2b">XV_HDMIRX1_AUX_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a983626c618f59a68cb6ef736c9f6d28a">XV_HDMIRX1_AUX_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a983626c618f59a68cb6ef736c9f6d28a"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a983626c618f59a68cb6ef736c9f6d28a">XV_HDMIRX1_AUX_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_AUX_CTRL_IE_MASK</div><div class="ttdoc">AUX Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:325</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_add9bba9228d3f408182b26777c21aa2b"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#add9bba9228d3f408182b26777c21aa2b">XV_HDMIRX1_AUX_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_AUX_CTRL_CLR_OFFSET</div><div class="ttdoc">AUX Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:312</div></div>
</div><!-- fragment -->
<p>This macro disables interrupts in the HDMI RX Auxiliary (AUX) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a1795c1a58886dfef4dff8d48d83781f5" title="This macro disables interrupts in the HDMI RX Auxiliary (AUX) peripheral. ">XV_HdmiRx1_AuxIntrDisable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="af5e8e60bd7c915758d1a6961901427cc"></a>
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          <td class="memname">#define XV_HdmiRx1_AuxIntrEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ac751b5b5be3fe003fe43f056f292bbf0">XV_HDMIRX1_AUX_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a983626c618f59a68cb6ef736c9f6d28a">XV_HDMIRX1_AUX_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ac751b5b5be3fe003fe43f056f292bbf0"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ac751b5b5be3fe003fe43f056f292bbf0">XV_HDMIRX1_AUX_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_AUX_CTRL_SET_OFFSET</div><div class="ttdoc">AUX Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:311</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a983626c618f59a68cb6ef736c9f6d28a"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a983626c618f59a68cb6ef736c9f6d28a">XV_HDMIRX1_AUX_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_AUX_CTRL_IE_MASK</div><div class="ttdoc">AUX Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:325</div></div>
</div><!-- fragment -->
<p>This macro enables interrupts in the HDMI RX Auxiliary (AUX) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#af5e8e60bd7c915758d1a6961901427cc" title="This macro enables interrupts in the HDMI RX Auxiliary (AUX) peripheral. ">XV_HdmiRx1_AuxIntrEnable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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<a class="anchor" id="a536f7ca1bc870452a33d8bf7fa54eb17"></a>
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          <td class="memname">#define XV_HdmiRx1_AxisEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Enable&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (Enable) { <a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">		XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#ab7fa4573aef8cdef877bb782670b5dd2">XV_HDMIRX1_PIO_OUT_AXIS_EN_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">        else { <a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">		XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#ab7fa4573aef8cdef877bb782670b5dd2">XV_HDMIRX1_PIO_OUT_AXIS_EN_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a9f3ee5ffefea5fea81b6278347ac0911"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_CLR_OFFSET</div><div class="ttdoc">PIO Out Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:92</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ab7fa4573aef8cdef877bb782670b5dd2"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ab7fa4573aef8cdef877bb782670b5dd2">XV_HDMIRX1_PIO_OUT_AXIS_EN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_AXIS_EN_MASK</div><div class="ttdoc">PIO Out Axis Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:121</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ada35683dde8266cadc45f975707d577b"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_SET_OFFSET</div><div class="ttdoc">PIO Out Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:91</div></div>
</div><!-- fragment -->
<p>This macro asserts or clears the AXIS enable output port. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance. </td></tr>
    <tr><td class="paramname">Reset</td><td>specifies TRUE/FALSE value to either assert or release HDMI RX reset.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The reset output of the PIO is inverted. When the system is in reset, the PIO output is cleared and this will reset the HDMI RX. Therefore, clearing the PIO reset output will assert the HDMI link and video reset. C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a536f7ca1bc870452a33d8bf7fa54eb17" title="This macro asserts or clears the AXIS enable output port. ">XV_HdmiRx1_AxisEnable(InstancePtr, Enable)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_Bridge_pixel</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">SetClr&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (SetClr) { <a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">		XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#ab38c46f5b81c2bfd313314921cf5c275">XV_HDMIRX1_PIO_OUT_BRIDGE_PIXEL_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">        else { <a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">		XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#ab38c46f5b81c2bfd313314921cf5c275">XV_HDMIRX1_PIO_OUT_BRIDGE_PIXEL_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ab38c46f5b81c2bfd313314921cf5c275"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ab38c46f5b81c2bfd313314921cf5c275">XV_HDMIRX1_PIO_OUT_BRIDGE_PIXEL_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_BRIDGE_PIXEL_MASK</div><div class="ttdoc">PIO Out Bridge_Pixel drop mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:129</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a9f3ee5ffefea5fea81b6278347ac0911"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_CLR_OFFSET</div><div class="ttdoc">PIO Out Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:92</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ada35683dde8266cadc45f975707d577b"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_SET_OFFSET</div><div class="ttdoc">PIO Out Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:91</div></div>
</div><!-- fragment -->
<p>This macro controls the Pixel Drop mode for video bridge. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Rx core instance. </td></tr>
    <tr><td class="paramname">SetClr</td><td>specifies TRUE/FALSE value to either enable or disable the Pixel Repitition.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a2b959c8cce4d462ec624a59d1aa6802c" title="This macro controls the Pixel Drop mode for video bridge. ">XV_HdmiRx1_Bridge_pixel(XV_HdmiRx1 *InstancePtr, u8 SetClr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_Bridge_yuv420</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">SetClr&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (SetClr) { <a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">		XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#af5b360bef2825b063ec1d6a4f5cfe55a">XV_HDMIRX1_PIO_OUT_BRIDGE_YUV420_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">        else { <a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">		XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#af5b360bef2825b063ec1d6a4f5cfe55a">XV_HDMIRX1_PIO_OUT_BRIDGE_YUV420_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a9f3ee5ffefea5fea81b6278347ac0911"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_CLR_OFFSET</div><div class="ttdoc">PIO Out Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:92</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_af5b360bef2825b063ec1d6a4f5cfe55a"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#af5b360bef2825b063ec1d6a4f5cfe55a">XV_HDMIRX1_PIO_OUT_BRIDGE_YUV420_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_BRIDGE_YUV420_MASK</div><div class="ttdoc">PIO Out Bridge_YUV420 mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:128</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ada35683dde8266cadc45f975707d577b"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_SET_OFFSET</div><div class="ttdoc">PIO Out Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:91</div></div>
</div><!-- fragment -->
<p>This macro controls the YUV420 mode for video bridge. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Rx core instance. </td></tr>
    <tr><td class="paramname">SetClr</td><td>specifies TRUE/FALSE value to either enable or disable the YUV 420 Support.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a8b431f0a256aba088876a8137c47400c" title="This macro controls the YUV420 mode for video bridge. ">XV_HdmiRx1_Bridge_yuv420(XV_HdmiRx1 *InstancePtr, u8 SetClr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_ClearAudioAcrUpdateEventEn</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>(InstancePtr-&gt;Config.BaseAddress, \</div>
<div class="line">                        <a class="code" href="xv__hdmirx1__hw_8h.html#ac3b08fa2ae41be9a6904419b439d79f3">XV_HDMIRX1_AUD_CTRL_CLR_OFFSET</a>, \</div>
<div class="line">                        <a class="code" href="xv__hdmirx1__hw_8h.html#acebfc50acd8328e43d89fd4d297eb9b7">XV_HDMIRX1_AUD_CTRL_ACR_UPD_EVT_EN_MASK</a>)</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_acebfc50acd8328e43d89fd4d297eb9b7"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#acebfc50acd8328e43d89fd4d297eb9b7">XV_HDMIRX1_AUD_CTRL_ACR_UPD_EVT_EN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_AUD_CTRL_ACR_UPD_EVT_EN_MASK</div><div class="ttdoc">AUD Control ACR Update Event Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:428</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ac3b08fa2ae41be9a6904419b439d79f3"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ac3b08fa2ae41be9a6904419b439d79f3">XV_HDMIRX1_AUD_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_AUD_CTRL_CLR_OFFSET</div><div class="ttdoc">AUD Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:420</div></div>
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<p>This macro disables ACR Update Event in the HDMI RX Audio (AUD) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_DdcDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a9cc9a4f86e3821f62a929d6d560a71d7">XV_HDMIRX1_DDC_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ad1701bdc9e14c9c171f210caee99219a">XV_HDMIRX1_DDC_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ad1701bdc9e14c9c171f210caee99219a"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ad1701bdc9e14c9c171f210caee99219a">XV_HDMIRX1_DDC_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_RUN_MASK</div><div class="ttdoc">DDC Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:271</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a9cc9a4f86e3821f62a929d6d560a71d7"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a9cc9a4f86e3821f62a929d6d560a71d7">XV_HDMIRX1_DDC_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_CLR_OFFSET</div><div class="ttdoc">DDC Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:259</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
</div><!-- fragment -->
<p>This macro disables the HDMI RX Display Data Channel (DDC) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#afa5c7f669b19e1b0f9cbad39adb674bc" title="This macro disables the HDMI RX Display Data Channel (DDC) peripheral. ">XV_HdmiRx1_DdcDisable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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          <td class="memname">#define XV_HdmiRx1_DdcEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a771754708a8fe2d29a65563db1a7a118">XV_HDMIRX1_DDC_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ad1701bdc9e14c9c171f210caee99219a">XV_HDMIRX1_DDC_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ad1701bdc9e14c9c171f210caee99219a"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ad1701bdc9e14c9c171f210caee99219a">XV_HDMIRX1_DDC_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_RUN_MASK</div><div class="ttdoc">DDC Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:271</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a771754708a8fe2d29a65563db1a7a118"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a771754708a8fe2d29a65563db1a7a118">XV_HDMIRX1_DDC_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_SET_OFFSET</div><div class="ttdoc">DDC Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:258</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
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<p>This macro enables the HDMI RX Display Data Channel (DDC) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a2fa160f04e804a5214822c2031bcce4a" title="This macro enables the HDMI RX Display Data Channel (DDC) peripheral. ">XV_HdmiRx1_DdcEnable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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          <td class="memname">#define XV_HdmiRx1_DdcHdcp14Mode</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a9cc9a4f86e3821f62a929d6d560a71d7">XV_HDMIRX1_DDC_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a49de50ec209773717034cf9cd694fdbb">XV_HDMIRX1_DDC_CTRL_HDCP_MODE_MASK</a>));</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a9cc9a4f86e3821f62a929d6d560a71d7"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a9cc9a4f86e3821f62a929d6d560a71d7">XV_HDMIRX1_DDC_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_CLR_OFFSET</div><div class="ttdoc">DDC Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:259</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a49de50ec209773717034cf9cd694fdbb"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a49de50ec209773717034cf9cd694fdbb">XV_HDMIRX1_DDC_CTRL_HDCP_MODE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_HDCP_MODE_MASK</div><div class="ttdoc">DDC Control HDCP mode mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:279</div></div>
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<p>This macro sets the DDC peripheral into HDCP 1.4 mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a0a1ce2053f275719061d178860e990e6" title="This macro sets the DDC peripheral into HDCP 1.4 mode. ">XV_HdmiRx1_DdcHdcp14Mode(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_DdcHdcp22Mode</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a771754708a8fe2d29a65563db1a7a118">XV_HDMIRX1_DDC_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a49de50ec209773717034cf9cd694fdbb">XV_HDMIRX1_DDC_CTRL_HDCP_MODE_MASK</a>));</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a771754708a8fe2d29a65563db1a7a118"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a771754708a8fe2d29a65563db1a7a118">XV_HDMIRX1_DDC_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_SET_OFFSET</div><div class="ttdoc">DDC Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:258</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a49de50ec209773717034cf9cd694fdbb"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a49de50ec209773717034cf9cd694fdbb">XV_HDMIRX1_DDC_CTRL_HDCP_MODE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_HDCP_MODE_MASK</div><div class="ttdoc">DDC Control HDCP mode mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:279</div></div>
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<p>This macro sets the DDC peripheral into HDCP 2.2 mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#aebc9674ef54135cb579c47b83ea51d56" title="This macro sets the DDC peripheral into HDCP 2.2 mode. ">XV_HdmiRx1_DdcHdcp22Mode(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_DdcHdcpClearReadMessageBuffer</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a771754708a8fe2d29a65563db1a7a118">XV_HDMIRX1_DDC_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ab3da38b5ded37f584afa3cdaa471ffc0">XV_HDMIRX1_DDC_CTRL_RMSG_CLR_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ab3da38b5ded37f584afa3cdaa471ffc0"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ab3da38b5ded37f584afa3cdaa471ffc0">XV_HDMIRX1_DDC_CTRL_RMSG_CLR_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_RMSG_CLR_MASK</div><div class="ttdoc">DDC Control read message clear mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:278</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a771754708a8fe2d29a65563db1a7a118"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a771754708a8fe2d29a65563db1a7a118">XV_HDMIRX1_DDC_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_SET_OFFSET</div><div class="ttdoc">DDC Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:258</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
</div><!-- fragment -->
<p>This macro clears the HDCP read message buffer in the DDC peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Rx core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XHdmiRx1_DdcHdcpClearReadMessageBuffer(XHdmi_Rx *InstancePtr) </dd></dl>

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<a class="anchor" id="a8f626ebfd672df8c3b3651857fbcba55"></a>
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          <td class="memname">#define XV_HdmiRx1_DdcHdcpClearWriteMessageBuffer</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a771754708a8fe2d29a65563db1a7a118">XV_HDMIRX1_DDC_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#adfbdf61fa82aba22cb7bb3240f6bdbfb">XV_HDMIRX1_DDC_CTRL_WMSG_CLR_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a771754708a8fe2d29a65563db1a7a118"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a771754708a8fe2d29a65563db1a7a118">XV_HDMIRX1_DDC_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_SET_OFFSET</div><div class="ttdoc">DDC Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:258</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_adfbdf61fa82aba22cb7bb3240f6bdbfb"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#adfbdf61fa82aba22cb7bb3240f6bdbfb">XV_HDMIRX1_DDC_CTRL_WMSG_CLR_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_WMSG_CLR_MASK</div><div class="ttdoc">DDC Control write message clear mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:277</div></div>
</div><!-- fragment -->
<p>This macro clears the HDCP write message buffer in the DDC peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Rx core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XHdmiRx1_DdcHdcpClearWriteMessageBuffer(XHdmi_Rx *InstancePtr) </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_DdcHdcpEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a771754708a8fe2d29a65563db1a7a118">XV_HDMIRX1_DDC_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a3b8e0eb851af6c285e4d2a0c9a338604">XV_HDMIRX1_DDC_CTRL_HDCP_EN_MASK</a>));</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a3b8e0eb851af6c285e4d2a0c9a338604"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a3b8e0eb851af6c285e4d2a0c9a338604">XV_HDMIRX1_DDC_CTRL_HDCP_EN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_HDCP_EN_MASK</div><div class="ttdoc">DDC Control HDCP enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:275</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a771754708a8fe2d29a65563db1a7a118"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a771754708a8fe2d29a65563db1a7a118">XV_HDMIRX1_DDC_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_SET_OFFSET</div><div class="ttdoc">DDC Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:258</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
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<p>This macro enables the HDCP in the DDC peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#ae85e61794d7039e19fe4ed0994af122a" title="This macro enables the HDCP in the DDC peripheral. ">XV_HdmiRx1_DdcHdcpEnable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_DdcIntrDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a9cc9a4f86e3821f62a929d6d560a71d7">XV_HDMIRX1_DDC_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a2e3e20ebe8b6d8378d84499355294b18">XV_HDMIRX1_DDC_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a2e3e20ebe8b6d8378d84499355294b18"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a2e3e20ebe8b6d8378d84499355294b18">XV_HDMIRX1_DDC_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_IE_MASK</div><div class="ttdoc">DDC Control Interrupt enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:272</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a9cc9a4f86e3821f62a929d6d560a71d7"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a9cc9a4f86e3821f62a929d6d560a71d7">XV_HDMIRX1_DDC_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_CLR_OFFSET</div><div class="ttdoc">DDC Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:259</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
</div><!-- fragment -->
<p>This macro disables interrupts in the HDMI RX Display Data Channel (DDC) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a454b5d814587e811db3529121a42dffe" title="This macro disables interrupts in the HDMI RX Display Data Channel (DDC) peripheral. ">XV_HdmiRx1_DdcIntrDisable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="a1c97d857d2d7737f4c9a25975e6cdab7"></a>
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          <td class="memname">#define XV_HdmiRx1_DdcIntrEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a771754708a8fe2d29a65563db1a7a118">XV_HDMIRX1_DDC_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a2e3e20ebe8b6d8378d84499355294b18">XV_HDMIRX1_DDC_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a2e3e20ebe8b6d8378d84499355294b18"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a2e3e20ebe8b6d8378d84499355294b18">XV_HDMIRX1_DDC_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_IE_MASK</div><div class="ttdoc">DDC Control Interrupt enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:272</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a771754708a8fe2d29a65563db1a7a118"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a771754708a8fe2d29a65563db1a7a118">XV_HDMIRX1_DDC_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_SET_OFFSET</div><div class="ttdoc">DDC Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:258</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
</div><!-- fragment -->
<p>This macro enables interrupts in the HDMI RX Display Data Channel (DDC) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a1c97d857d2d7737f4c9a25975e6cdab7" title="This macro enables interrupts in the HDMI RX Display Data Channel (DDC) peripheral. ">XV_HdmiRx1_DdcIntrEnable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="ad2801bbba5e4a3492373d59f783bc0b4"></a>
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          <td class="memname">#define XV_HdmiRx1_DdcScdcClear</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ <a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">	XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a771754708a8fe2d29a65563db1a7a118">XV_HDMIRX1_DDC_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ad67f0253e5d43f97490f485ff58d7de4">XV_HDMIRX1_DDC_CTRL_SCDC_CLR_MASK</a>)); \</div>
<div class="line">        usleep(50);<a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">	XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a9cc9a4f86e3821f62a929d6d560a71d7">XV_HDMIRX1_DDC_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ad67f0253e5d43f97490f485ff58d7de4">XV_HDMIRX1_DDC_CTRL_SCDC_CLR_MASK</a>)); <a class="code" href="xv__hdmirx1_8h.html#ab17e4f96ebbe6785b411233165de859a">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1_8h.html#ab17e4f96ebbe6785b411233165de859a">	XV_HdmiRx1_FrlDdcWriteField</a>(InstancePtr, XV_HDMIRX1_SCDCFIELD_FLT_READY,\</div>
<div class="line">                                    1);<a class="code" href="xv__hdmirx1_8h.html#ab17e4f96ebbe6785b411233165de859a">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1_8h.html#ab17e4f96ebbe6785b411233165de859a">	XV_HdmiRx1_FrlDdcWriteField</a>(InstancePtr,XV_HDMIRX1_SCDCFIELD_SINK_VER, \</div>
<div class="line">                                    1);\</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ad67f0253e5d43f97490f485ff58d7de4"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ad67f0253e5d43f97490f485ff58d7de4">XV_HDMIRX1_DDC_CTRL_SCDC_CLR_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_SCDC_CLR_MASK</div><div class="ttdoc">DDC Control SCDC clear mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:276</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a771754708a8fe2d29a65563db1a7a118"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a771754708a8fe2d29a65563db1a7a118">XV_HDMIRX1_DDC_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_SET_OFFSET</div><div class="ttdoc">DDC Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:258</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a9cc9a4f86e3821f62a929d6d560a71d7"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a9cc9a4f86e3821f62a929d6d560a71d7">XV_HDMIRX1_DDC_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_CLR_OFFSET</div><div class="ttdoc">DDC Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:259</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1_8h_html_ab17e4f96ebbe6785b411233165de859a"><div class="ttname"><a href="xv__hdmirx1_8h.html#ab17e4f96ebbe6785b411233165de859a">XV_HdmiRx1_FrlDdcWriteField</a></div><div class="ttdeci">int XV_HdmiRx1_FrlDdcWriteField(XV_HdmiRx1 *InstancePtr, XV_HdmiRx1_FrlScdcFieldType Field, u8 Value)</div><div class="ttdoc">This function writes the specified FRL SCDC Field. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_frl.c:1394</div></div>
</div><!-- fragment -->
<p>This macro clears the SCDC registers in the DDC peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#ad2801bbba5e4a3492373d59f783bc0b4" title="This macro clears the SCDC registers in the DDC peripheral. ">XV_HdmiRx1_DdcScdcClear(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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          <td class="memname">#define XV_HdmiRx1_DdcScdcEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a771754708a8fe2d29a65563db1a7a118">XV_HDMIRX1_DDC_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#af1c3bf86b1639762038aecd48e26e58e">XV_HDMIRX1_DDC_CTRL_SCDC_EN_MASK</a>));</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a771754708a8fe2d29a65563db1a7a118"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a771754708a8fe2d29a65563db1a7a118">XV_HDMIRX1_DDC_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_SET_OFFSET</div><div class="ttdoc">DDC Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:258</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_af1c3bf86b1639762038aecd48e26e58e"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#af1c3bf86b1639762038aecd48e26e58e">XV_HDMIRX1_DDC_CTRL_SCDC_EN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_DDC_CTRL_SCDC_EN_MASK</div><div class="ttdoc">DDC Control SCDC enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:274</div></div>
</div><!-- fragment -->
<p>This macro enables the SCDC in the DDC peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a29847cccb96616c7a70252a0ae823e67" title="This macro enables the SCDC in the DDC peripheral. ">XV_HdmiRx1_DdcScdcEnable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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<a class="anchor" id="a68af32f4a9ad2ed19166d4695ac73d73"></a>
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          <td class="memname">#define XV_HdmiRx1_DynHDR_DM_Disable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            <a class="code" href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a>, \</div>
<div class="line">                            <a class="code" href="xv__hdmirx1__hw_8h.html#a7e60d62918e48ee2e27bfc0064d3863d">XV_HDMIRX1_PIO_OUT_DYN_HDR_DM_EN_MASK</a>)</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a9f3ee5ffefea5fea81b6278347ac0911"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_CLR_OFFSET</div><div class="ttdoc">PIO Out Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:92</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a7e60d62918e48ee2e27bfc0064d3863d"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a7e60d62918e48ee2e27bfc0064d3863d">XV_HDMIRX1_PIO_OUT_DYN_HDR_DM_EN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_DYN_HDR_DM_EN_MASK</div><div class="ttdoc">PIO Out Dynamic HDR Data Mover enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:147</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
</div><!-- fragment -->
<p>This macro disables the data mover for Dynamic HDR. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a68af32f4a9ad2ed19166d4695ac73d73" title="This macro disables the data mover for Dynamic HDR. ">XV_HdmiRx1_DynHDR_DM_Disable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="af65e0cebc04f0d1da21b84d1b64237ce"></a>
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          <td class="memname">#define XV_HdmiRx1_DynHDR_DM_Enable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            <a class="code" href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a>, \</div>
<div class="line">                            <a class="code" href="xv__hdmirx1__hw_8h.html#a7e60d62918e48ee2e27bfc0064d3863d">XV_HDMIRX1_PIO_OUT_DYN_HDR_DM_EN_MASK</a>)</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a7e60d62918e48ee2e27bfc0064d3863d"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a7e60d62918e48ee2e27bfc0064d3863d">XV_HDMIRX1_PIO_OUT_DYN_HDR_DM_EN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_DYN_HDR_DM_EN_MASK</div><div class="ttdoc">PIO Out Dynamic HDR Data Mover enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:147</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ada35683dde8266cadc45f975707d577b"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_SET_OFFSET</div><div class="ttdoc">PIO Out Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:91</div></div>
</div><!-- fragment -->
<p>This macro enables the data mover for Dynamic HDR. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#af65e0cebc04f0d1da21b84d1b64237ce" title="This macro enables the data mover for Dynamic HDR. ">XV_HdmiRx1_DynHDR_DM_Enable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_GetAudioChannels</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td>&#160;&#160;&#160;(InstancePtr)-&gt;Stream.Audio.Channels</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro returns the number of active audio channels. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Number of active audio channels.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xv__hdmirx1_8h.html#a409088a9f753dff7025b7f5779eb3206" title="This macro returns the number of active audio channels. ">XV_HdmiRx1_GetAudioChannels(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_GetTime10Ms</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td>&#160;&#160;&#160;(InstancePtr)-&gt;Config.AxiLiteClkFreq/100</td>
        </tr>
      </table>
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<p>This macro returns the clock cycles required to count up to 10Ms with respect to AXI Lite Frequency. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XV_HdmiRX1 core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_GetTime16Ms</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td>&#160;&#160;&#160;((InstancePtr)-&gt;Config.AxiLiteClkFreq * 10) / 625</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro returns the clock cycles required to count up to 16Ms with respect to AXI Lite Frequency. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XV_HdmiRX1 core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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<a class="anchor" id="af5225d7549628e39d200cb5d6f0ef44a"></a>
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          <td class="memname">#define XV_HdmiRx1_GetTime1S</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td>&#160;&#160;&#160;(InstancePtr)-&gt;Config.AxiLiteClkFreq</td>
        </tr>
      </table>
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<p>This macro returns the clock cycles required to count up to 1s with respect to AXI Lite Frequency. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XV_HdmiRX1 core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

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<a class="anchor" id="ac4d147dab9255ea47ee7c5e5f9a45a7e"></a>
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          <td class="memname">#define XV_HdmiRx1_GetTime200Ms</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td>&#160;&#160;&#160;(InstancePtr)-&gt;Config.AxiLiteClkFreq/5</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro returns the clock cycles required to count up to 200Ms with respect to AXI Lite Frequency. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XV_HdmiRX1 core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_GetTmr1Value</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
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<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                           (<a class="code" href="xv__hdmirx1__hw_8h.html#a293fd830851198f7e914a854331b5896">XV_HDMIRX1_TMR1_CNT_OFFSET</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a293fd830851198f7e914a854331b5896"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a293fd830851198f7e914a854331b5896">XV_HDMIRX1_TMR1_CNT_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR1_CNT_OFFSET</div><div class="ttdoc">TMR Counter Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:196</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a851cb0524c797d3ce8380b1c27b9a17f"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a></div><div class="ttdeci">#define XV_HdmiRx1_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads a value from a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:783</div></div>
</div><!-- fragment -->
<p>This macro reads the HDMI RX timer peripheral's remaining timer counter value. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a7de25fdf8166abb9ae7a4f9a3d7b5555" title="This macro reads the HDMI RX timer peripheral&#39;s remaining timer counter value. ">XV_HdmiRx1_GetTmr1Value(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#ad8f801766bca274f8235adde45ddc085">XV_HdmiRx1_ConfigFrlLtpDetection()</a>.</p>

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          <td class="memname">#define XV_HdmiRx1_GetTmr2Value</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                           (<a class="code" href="xv__hdmirx1__hw_8h.html#aeae47d24687bc43e32160a9308182746">XV_HDMIRX1_TMR2_CNT_OFFSET</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_aeae47d24687bc43e32160a9308182746"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#aeae47d24687bc43e32160a9308182746">XV_HDMIRX1_TMR2_CNT_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR2_CNT_OFFSET</div><div class="ttdoc">TMR Counter Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:197</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a851cb0524c797d3ce8380b1c27b9a17f"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a></div><div class="ttdeci">#define XV_HdmiRx1_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads a value from a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:783</div></div>
</div><!-- fragment -->
<p>This macro reads the HDMI RX timer peripheral's remaining timer counter value. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#ab35c7e83b036ed9da616b6493f37cf74" title="This macro reads the HDMI RX timer peripheral&#39;s remaining timer counter value. ">XV_HdmiRx1_GetTmr2Value(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_GetTmr3Value</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                           (<a class="code" href="xv__hdmirx1__hw_8h.html#ae3314caa4470dc986d1d7a50f1de62c9">XV_HDMIRX1_TMR3_CNT_OFFSET</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ae3314caa4470dc986d1d7a50f1de62c9"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ae3314caa4470dc986d1d7a50f1de62c9">XV_HDMIRX1_TMR3_CNT_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR3_CNT_OFFSET</div><div class="ttdoc">TMR Counter Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:198</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a851cb0524c797d3ce8380b1c27b9a17f"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a></div><div class="ttdeci">#define XV_HdmiRx1_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads a value from a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:783</div></div>
</div><!-- fragment -->
<p>This macro reads the HDMI RX timer peripheral's remaining timer counter value. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#abe903d75443ce36e9868f719091ebb05" title="This macro reads the HDMI RX timer peripheral&#39;s remaining timer counter value. ">XV_HdmiRx1_GetTmr3Value(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_GetTmr4Value</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                           (<a class="code" href="xv__hdmirx1__hw_8h.html#a2b45e7f59deb365e580565110ec1be4e">XV_HDMIRX1_TMR4_CNT_OFFSET</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a2b45e7f59deb365e580565110ec1be4e"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a2b45e7f59deb365e580565110ec1be4e">XV_HDMIRX1_TMR4_CNT_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR4_CNT_OFFSET</div><div class="ttdoc">TMR Counter Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:199</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a851cb0524c797d3ce8380b1c27b9a17f"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a></div><div class="ttdeci">#define XV_HdmiRx1_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads a value from a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:783</div></div>
</div><!-- fragment -->
<p>This macro reads the HDMI RX timer peripheral's remaining timer counter value. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a2138cb9268f7da591da9f9ab73d1e735" title="This macro reads the HDMI RX timer peripheral&#39;s remaining timer counter value. ">XV_HdmiRx1_GetTmr4Value(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_GetVersion</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                           (<a class="code" href="xv__hdmirx1__hw_8h.html#a8b63858c4f1f73528819cac7258bc730">XV_HDMIRX1_VER_VERSION_OFFSET</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a8b63858c4f1f73528819cac7258bc730"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a8b63858c4f1f73528819cac7258bc730">XV_HDMIRX1_VER_VERSION_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_VER_VERSION_OFFSET</div><div class="ttdoc">VER Version Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:45</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a851cb0524c797d3ce8380b1c27b9a17f"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a></div><div class="ttdeci">#define XV_HdmiRx1_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads a value from a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:783</div></div>
</div><!-- fragment -->
<p>This macro reads the RX version. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_RX core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>RX version.</dd></dl>
<p>*note C-style signature: u32 <a class="el" href="xv__hdmirx1_8h.html#a2c43beaac345faea28b787d8c40e5741" title="This macro reads the RX version. ">XV_HdmiRx1_GetVersion(XV_HdmiRx1 *InstancePtr)</a> </p>

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          <td class="memname">#define XV_HDMIRX1_H_</td>
        </tr>
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<p>Prevent circular inclusions by using protection macros. </p>

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          <td class="memname">#define XV_HdmiRx1_IsAudioActive</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td>&#160;&#160;&#160;(InstancePtr)-&gt;Stream.Audio.Active</td>
        </tr>
      </table>
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<p>This macro returns true is the audio stream is active else false. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>TRUE if the audio stream is active, FALSE if it is not.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xv__hdmirx1_8h.html#aba75843e30381249f64cc4fa194aa13d" title="This macro returns true is the audio stream is active else false. ">XV_HdmiRx1_IsAudioActive(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_LinkEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">SetClr&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (SetClr) { <a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">		XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#a9664bc1a8eba4759abae05a526070145">XV_HDMIRX1_PIO_OUT_LNK_EN_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">        else { <a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">		XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#a9664bc1a8eba4759abae05a526070145">XV_HDMIRX1_PIO_OUT_LNK_EN_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a9f3ee5ffefea5fea81b6278347ac0911"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_CLR_OFFSET</div><div class="ttdoc">PIO Out Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:92</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a9664bc1a8eba4759abae05a526070145"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a9664bc1a8eba4759abae05a526070145">XV_HDMIRX1_PIO_OUT_LNK_EN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_LNK_EN_MASK</div><div class="ttdoc">PIO Out video enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:113</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ada35683dde8266cadc45f975707d577b"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_SET_OFFSET</div><div class="ttdoc">PIO Out Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:91</div></div>
</div><!-- fragment -->
<p>This macro asserts or clears the HDMI RX link enable. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance. </td></tr>
    <tr><td class="paramname">SetClr</td><td>specifies TRUE/FALSE value to either assert or release HDMI RX link enable.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a33e7dd96086ade48b9cf40729dc5e997" title="This macro asserts or clears the HDMI RX reset. ">XV_HdmiRx1_Reset(XV_HdmiRx1 *InstancePtr, u8 SetClr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_LinkIntrDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a0ea4dac580c41d65c59984742c93fcaf">XV_HDMIRX1_LNKSTA_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ae1e79cbc38e074f009b92ccb96660faf">XV_HDMIRX1_LNKSTA_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ae1e79cbc38e074f009b92ccb96660faf"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ae1e79cbc38e074f009b92ccb96660faf">XV_HDMIRX1_LNKSTA_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_LNKSTA_CTRL_IE_MASK</div><div class="ttdoc">LNKSTA Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:460</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a0ea4dac580c41d65c59984742c93fcaf"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a0ea4dac580c41d65c59984742c93fcaf">XV_HDMIRX1_LNKSTA_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_LNKSTA_CTRL_CLR_OFFSET</div><div class="ttdoc">LNKSTA Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:448</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
</div><!-- fragment -->
<p>This macro disable interrupt in the HDMI RX Link Status (LNKSTA) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#afaa36adac08f538ed818974141158dbd" title="This macro disable interrupt in the HDMI RX Link Status (LNKSTA) peripheral. ">XV_HdmiRx1_LinkIntrDisable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_LinkIntrEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a23eec7113adc6c29ad2a46331582ae29">XV_HDMIRX1_LNKSTA_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ae1e79cbc38e074f009b92ccb96660faf">XV_HDMIRX1_LNKSTA_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ae1e79cbc38e074f009b92ccb96660faf"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ae1e79cbc38e074f009b92ccb96660faf">XV_HDMIRX1_LNKSTA_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_LNKSTA_CTRL_IE_MASK</div><div class="ttdoc">LNKSTA Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:460</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a23eec7113adc6c29ad2a46331582ae29"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a23eec7113adc6c29ad2a46331582ae29">XV_HDMIRX1_LNKSTA_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_LNKSTA_CTRL_SET_OFFSET</div><div class="ttdoc">LNKSTA Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:447</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
</div><!-- fragment -->
<p>This macro enables interrupt in the HDMI RX Link Status (LNKSTA) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a1f63ca19bbee2e5a8bdc3a935063a764" title="This macro enables interrupt in the HDMI RX Link Status (LNKSTA) peripheral. ">XV_HdmiRx1_LinkIntrEnable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_LnkstaDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a0ea4dac580c41d65c59984742c93fcaf">XV_HDMIRX1_LNKSTA_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a4b0867e14c060bc025e48a9ad4fd4384">XV_HDMIRX1_LNKSTA_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a0ea4dac580c41d65c59984742c93fcaf"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a0ea4dac580c41d65c59984742c93fcaf">XV_HDMIRX1_LNKSTA_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_LNKSTA_CTRL_CLR_OFFSET</div><div class="ttdoc">LNKSTA Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:448</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a4b0867e14c060bc025e48a9ad4fd4384"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a4b0867e14c060bc025e48a9ad4fd4384">XV_HDMIRX1_LNKSTA_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_LNKSTA_CTRL_RUN_MASK</div><div class="ttdoc">LNKSTA Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:459</div></div>
</div><!-- fragment -->
<p>This macro disables the HDMI RX Link Status (LNKSTA) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XV_HdmiRx1_LinkstaDisable(XV_HdmiRx1 *InstancePtr) </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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<a class="anchor" id="a82a49f48613a311ebd77b7c06d774287"></a>
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          <td class="memname">#define XV_HdmiRx1_LnkstaEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a23eec7113adc6c29ad2a46331582ae29">XV_HDMIRX1_LNKSTA_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a4b0867e14c060bc025e48a9ad4fd4384">XV_HDMIRX1_LNKSTA_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a23eec7113adc6c29ad2a46331582ae29"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a23eec7113adc6c29ad2a46331582ae29">XV_HDMIRX1_LNKSTA_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_LNKSTA_CTRL_SET_OFFSET</div><div class="ttdoc">LNKSTA Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:447</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a4b0867e14c060bc025e48a9ad4fd4384"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a4b0867e14c060bc025e48a9ad4fd4384">XV_HDMIRX1_LNKSTA_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_LNKSTA_CTRL_RUN_MASK</div><div class="ttdoc">LNKSTA Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:459</div></div>
</div><!-- fragment -->
<p>This macro enables the HDMI RX Link Status (LNKSTA) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XV_HdmiRx1_LinkstaEnable(XV_HdmiRx1 *InstancePtr) </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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<a class="anchor" id="a4d57a91b21377a43a2692f64564bc121"></a>
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          <td class="memname">#define XV_HdmiRx1_PioDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ab783565a557552b6340347c74fa21ad9">XV_HDMIRX1_PIO_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a9ba54758033579b93394c923fa15dceb">XV_HDMIRX1_PIO_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ab783565a557552b6340347c74fa21ad9"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ab783565a557552b6340347c74fa21ad9">XV_HDMIRX1_PIO_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_CTRL_CLR_OFFSET</div><div class="ttdoc">PIO Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:88</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a9ba54758033579b93394c923fa15dceb"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a9ba54758033579b93394c923fa15dceb">XV_HDMIRX1_PIO_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_CTRL_RUN_MASK</div><div class="ttdoc">PIO Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:104</div></div>
</div><!-- fragment -->
<p>This macro disables the HDMI RX PIO peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a4d57a91b21377a43a2692f64564bc121" title="This macro disables the HDMI RX PIO peripheral. ">XV_HdmiRx1_PioDisable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx1_8h.html#aacd8eb82c28cab7d1e72d51f7e4923b8">XV_HdmiRx1_Stop()</a>.</p>

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<a class="anchor" id="ab1af2cce1f2ff3ae52dfb4cfbcd9a436"></a>
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          <td class="memname">#define XV_HdmiRx1_PioEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#aad7f2e6a3f83a5b545340458f0d696ca">XV_HDMIRX1_PIO_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a9ba54758033579b93394c923fa15dceb">XV_HDMIRX1_PIO_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_aad7f2e6a3f83a5b545340458f0d696ca"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#aad7f2e6a3f83a5b545340458f0d696ca">XV_HDMIRX1_PIO_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_CTRL_SET_OFFSET</div><div class="ttdoc">PIO Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:87</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a9ba54758033579b93394c923fa15dceb"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a9ba54758033579b93394c923fa15dceb">XV_HDMIRX1_PIO_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_CTRL_RUN_MASK</div><div class="ttdoc">PIO Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:104</div></div>
</div><!-- fragment -->
<p>This macro enables the HDMI RX PIO peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#ab1af2cce1f2ff3ae52dfb4cfbcd9a436" title="This macro enables the HDMI RX PIO peripheral. ">XV_HdmiRx1_PioEnable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a331430d0474344d993eb016fca535e65">XV_HdmiRx1_Start()</a>.</p>

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<a class="anchor" id="ae5f391082b5e60a7ea25086124900070"></a>
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          <td class="memname">#define XV_HdmiRx1_PioIntrDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ab783565a557552b6340347c74fa21ad9">XV_HDMIRX1_PIO_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ab295c07286c024627e6b5dd1abc99451">XV_HDMIRX1_PIO_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ab295c07286c024627e6b5dd1abc99451"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ab295c07286c024627e6b5dd1abc99451">XV_HDMIRX1_PIO_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_CTRL_IE_MASK</div><div class="ttdoc">PIO Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:105</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ab783565a557552b6340347c74fa21ad9"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ab783565a557552b6340347c74fa21ad9">XV_HDMIRX1_PIO_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_CTRL_CLR_OFFSET</div><div class="ttdoc">PIO Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:88</div></div>
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<p>This macro disables interrupts in the HDMI RX PIO peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#ae5f391082b5e60a7ea25086124900070" title="This macro disables interrupts in the HDMI RX PIO peripheral. ">XV_HdmiRx1_PioIntrDisable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx1_8h.html#aacd8eb82c28cab7d1e72d51f7e4923b8">XV_HdmiRx1_Stop()</a>.</p>

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          <td class="memname">#define XV_HdmiRx1_PioIntrEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#aad7f2e6a3f83a5b545340458f0d696ca">XV_HDMIRX1_PIO_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ab295c07286c024627e6b5dd1abc99451">XV_HDMIRX1_PIO_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_aad7f2e6a3f83a5b545340458f0d696ca"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#aad7f2e6a3f83a5b545340458f0d696ca">XV_HDMIRX1_PIO_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_CTRL_SET_OFFSET</div><div class="ttdoc">PIO Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:87</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ab295c07286c024627e6b5dd1abc99451"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ab295c07286c024627e6b5dd1abc99451">XV_HDMIRX1_PIO_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_CTRL_IE_MASK</div><div class="ttdoc">PIO Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:105</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
</div><!-- fragment -->
<p>This macro enables interrupts in the HDMI RX PIO peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a5ec3cb1a32c4e030d365023832bba3e2" title="This macro enables interrupts in the HDMI RX PIO peripheral. ">XV_HdmiRx1_PioIntrEnable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a331430d0474344d993eb016fca535e65">XV_HdmiRx1_Start()</a>.</p>

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          <td class="memname">#define XV_HdmiRx1_Reset</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Reset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (Reset) { <a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">		XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#aca9ae5b99ad8d51e238bd4837a8cc2da">XV_HDMIRX1_PIO_OUT_RESET_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">        else { <a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">		XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#aca9ae5b99ad8d51e238bd4837a8cc2da">XV_HDMIRX1_PIO_OUT_RESET_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a9f3ee5ffefea5fea81b6278347ac0911"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_CLR_OFFSET</div><div class="ttdoc">PIO Out Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:92</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_aca9ae5b99ad8d51e238bd4837a8cc2da"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#aca9ae5b99ad8d51e238bd4837a8cc2da">XV_HDMIRX1_PIO_OUT_RESET_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_RESET_MASK</div><div class="ttdoc">PIO Out Reset mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:112</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ada35683dde8266cadc45f975707d577b"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_SET_OFFSET</div><div class="ttdoc">PIO Out Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:91</div></div>
</div><!-- fragment -->
<p>This macro asserts or clears the HDMI RX reset. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance. </td></tr>
    <tr><td class="paramname">Reset</td><td>specifies TRUE/FALSE value to either assert or release HDMI RX reset.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The reset output of the PIO is inverted. When the system is in reset, the PIO output is cleared and this will reset the HDMI RX. Therefore, clearing the PIO reset output will assert the HDMI link and video reset. C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a33e7dd96086ade48b9cf40729dc5e997" title="This macro asserts or clears the HDMI RX reset. ">XV_HdmiRx1_Reset(XV_HdmiRx1 *InstancePtr, u8 Reset)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_SetAudioAcrUpdateEventEn</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>(InstancePtr-&gt;Config.BaseAddress, \</div>
<div class="line">                        <a class="code" href="xv__hdmirx1__hw_8h.html#a6144291d33bdfd02d9077042fb6a5f0d">XV_HDMIRX1_AUD_CTRL_SET_OFFSET</a>, \</div>
<div class="line">                        <a class="code" href="xv__hdmirx1__hw_8h.html#acebfc50acd8328e43d89fd4d297eb9b7">XV_HDMIRX1_AUD_CTRL_ACR_UPD_EVT_EN_MASK</a>)</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a6144291d33bdfd02d9077042fb6a5f0d"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a6144291d33bdfd02d9077042fb6a5f0d">XV_HDMIRX1_AUD_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_AUD_CTRL_SET_OFFSET</div><div class="ttdoc">AUD Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:419</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_acebfc50acd8328e43d89fd4d297eb9b7"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#acebfc50acd8328e43d89fd4d297eb9b7">XV_HDMIRX1_AUD_CTRL_ACR_UPD_EVT_EN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_AUD_CTRL_ACR_UPD_EVT_EN_MASK</div><div class="ttdoc">AUD Control ACR Update Event Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:428</div></div>
</div><!-- fragment -->
<p>This macro enables ACR Update Event in the HDMI RX Audio (AUD) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_SetScrambler</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">SetClr&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (SetClr) { <a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">		XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#a373757bf8fb4bca95302a14fc014a878">XV_HDMIRX1_PIO_OUT_SCRM_MASK</a>)); \</div>
<div class="line">                (InstancePtr)-&gt;Stream.IsScrambled = (TRUE); \</div>
<div class="line">        } \</div>
<div class="line">        else { <a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">		XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#a373757bf8fb4bca95302a14fc014a878">XV_HDMIRX1_PIO_OUT_SCRM_MASK</a>)); \</div>
<div class="line">                (InstancePtr)-&gt;Stream.IsScrambled = (FALSE); \</div>
<div class="line">        } <a class="code" href="xv__hdmirx1_8h.html#ab17e4f96ebbe6785b411233165de859a">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1_8h.html#ab17e4f96ebbe6785b411233165de859a">	XV_HdmiRx1_FrlDdcWriteField</a>((InstancePtr), \</div>
<div class="line">                                    XV_HDMIRX1_SCDCFIELD_SCRAMBLER_STAT, \</div>
<div class="line">                                    SetClr); \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a9f3ee5ffefea5fea81b6278347ac0911"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_CLR_OFFSET</div><div class="ttdoc">PIO Out Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:92</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1_8h_html_ab17e4f96ebbe6785b411233165de859a"><div class="ttname"><a href="xv__hdmirx1_8h.html#ab17e4f96ebbe6785b411233165de859a">XV_HdmiRx1_FrlDdcWriteField</a></div><div class="ttdeci">int XV_HdmiRx1_FrlDdcWriteField(XV_HdmiRx1 *InstancePtr, XV_HdmiRx1_FrlScdcFieldType Field, u8 Value)</div><div class="ttdoc">This function writes the specified FRL SCDC Field. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_frl.c:1394</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a373757bf8fb4bca95302a14fc014a878"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a373757bf8fb4bca95302a14fc014a878">XV_HDMIRX1_PIO_OUT_SCRM_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_SCRM_MASK</div><div class="ttdoc">PIO Out Scrambler mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:127</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ada35683dde8266cadc45f975707d577b"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_SET_OFFSET</div><div class="ttdoc">PIO Out Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:91</div></div>
</div><!-- fragment -->
<p>This macro controls the HDMI RX Scrambler. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Rx core instance. </td></tr>
    <tr><td class="paramname">SetClr</td><td>specifies TRUE/FALSE value to either enable or disable the scrambler.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a3b0e4a6f27c287db2e8876157c1675ee" title="This macro controls the HDMI RX Scrambler. ">XV_HdmiRx1_SetScrambler(XV_HdmiRx1 *InstancePtr, u8 SetClr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_Tmr1Disable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
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<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a1cdf2bc260e7b4039352ef7cea5638b9">XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</a>),\</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a4971c7cbae30577c586eb34bddec2aac">XV_HDMIRX1_TMR1_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a4971c7cbae30577c586eb34bddec2aac"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a4971c7cbae30577c586eb34bddec2aac">XV_HDMIRX1_TMR1_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR1_CTRL_RUN_MASK</div><div class="ttdoc">TMR Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:202</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a1cdf2bc260e7b4039352ef7cea5638b9"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a1cdf2bc260e7b4039352ef7cea5638b9">XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</div><div class="ttdoc">TMR Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:194</div></div>
</div><!-- fragment -->
<p>This macro disables the HDMI RX timer peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#aec115cc3973ecedde65e4b11d3ad5b5b" title="This macro disables the HDMI RX timer peripheral. ">XV_HdmiRx1_Tmr1Disable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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          <td class="memname">#define XV_HdmiRx1_Tmr1Enable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a3d6d8df87e3d66f70c7517431b791a10">XV_HDMIRX1_TMR_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a4971c7cbae30577c586eb34bddec2aac">XV_HDMIRX1_TMR1_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a4971c7cbae30577c586eb34bddec2aac"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a4971c7cbae30577c586eb34bddec2aac">XV_HDMIRX1_TMR1_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR1_CTRL_RUN_MASK</div><div class="ttdoc">TMR Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:202</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a3d6d8df87e3d66f70c7517431b791a10"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a3d6d8df87e3d66f70c7517431b791a10">XV_HDMIRX1_TMR_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR_CTRL_SET_OFFSET</div><div class="ttdoc">TMR Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:193</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
</div><!-- fragment -->
<p>This macro enables the HDMI RX timer peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a056971e8df07e73576859f1d25eb5b96" title="This macro enables the HDMI RX timer peripheral. ">XV_HdmiRx1_Tmr1Enable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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          <td class="memname">#define XV_HdmiRx1_Tmr1IntrDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a1cdf2bc260e7b4039352ef7cea5638b9">XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ac3f7fead56ecd78e386866c94c088e4b">XV_HDMIRX1_TMR1_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ac3f7fead56ecd78e386866c94c088e4b"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ac3f7fead56ecd78e386866c94c088e4b">XV_HDMIRX1_TMR1_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR1_CTRL_IE_MASK</div><div class="ttdoc">TMR Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:203</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a1cdf2bc260e7b4039352ef7cea5638b9"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a1cdf2bc260e7b4039352ef7cea5638b9">XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</div><div class="ttdoc">TMR Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:194</div></div>
</div><!-- fragment -->
<p>This macro disables interrupt in the HDMI RX timer peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a267240b43d2cadda19be932109867557" title="This macro disables interrupt in the HDMI RX timer peripheral. ">XV_HdmiRx1_Tmr1IntrDisable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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<a class="anchor" id="a27d61d0271f92f32b92971dcd726c2ca"></a>
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          <td class="memname">#define XV_HdmiRx1_Tmr1IntrEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a3d6d8df87e3d66f70c7517431b791a10">XV_HDMIRX1_TMR_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ac3f7fead56ecd78e386866c94c088e4b">XV_HDMIRX1_TMR1_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a3d6d8df87e3d66f70c7517431b791a10"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a3d6d8df87e3d66f70c7517431b791a10">XV_HDMIRX1_TMR_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR_CTRL_SET_OFFSET</div><div class="ttdoc">TMR Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:193</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ac3f7fead56ecd78e386866c94c088e4b"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ac3f7fead56ecd78e386866c94c088e4b">XV_HDMIRX1_TMR1_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR1_CTRL_IE_MASK</div><div class="ttdoc">TMR Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:203</div></div>
</div><!-- fragment -->
<p>This macro enables interrupts in the HDMI RX timer peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XV_HdmiRx1_TmrIntrEnable(XV_HdmiRx1 *InstancePtr) </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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<a class="anchor" id="aaa7bbaf2ae1157d275c4963c2f11cd16"></a>
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          <td class="memname">#define XV_HdmiRx1_Tmr1Start</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Value&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a293fd830851198f7e914a854331b5896">XV_HDMIRX1_TMR1_CNT_OFFSET</a>), (u32)(Value))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a293fd830851198f7e914a854331b5896"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a293fd830851198f7e914a854331b5896">XV_HDMIRX1_TMR1_CNT_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR1_CNT_OFFSET</div><div class="ttdoc">TMR Counter Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:196</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
</div><!-- fragment -->
<p>This macro starts the HDMI RX timer peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#aaa7bbaf2ae1157d275c4963c2f11cd16" title="This macro starts the HDMI RX timer peripheral. ">XV_HdmiRx1_Tmr1Start(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#aa8fec3226e7abab9b6a14251bd8705ba">XV_HdmiRx1_SetFrl10MicroSecondsTimer()</a>, and <a class="el" href="xv__hdmirx1_8h.html#af10ef171597554725eb963e6ee83278b">XV_HdmiRx1_TmrStartMs()</a>.</p>

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          <td class="memname">#define XV_HdmiRx1_Tmr2Disable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a1cdf2bc260e7b4039352ef7cea5638b9">XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</a>),\</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a2efd70def06239d90d9cfa77a554b478">XV_HDMIRX1_TMR2_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a2efd70def06239d90d9cfa77a554b478"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a2efd70def06239d90d9cfa77a554b478">XV_HDMIRX1_TMR2_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR2_CTRL_RUN_MASK</div><div class="ttdoc">TMR Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:204</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a1cdf2bc260e7b4039352ef7cea5638b9"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a1cdf2bc260e7b4039352ef7cea5638b9">XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</div><div class="ttdoc">TMR Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:194</div></div>
</div><!-- fragment -->
<p>This macro disables the HDMI RX timer peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a1faa4df9824550b8f828d68597ddd2c1" title="This macro disables the HDMI RX timer peripheral. ">XV_HdmiRx1_Tmr2Disable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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<a class="anchor" id="a015741105c8cf02b20e69e03b65ccc71"></a>
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          <td class="memname">#define XV_HdmiRx1_Tmr2Enable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a3d6d8df87e3d66f70c7517431b791a10">XV_HDMIRX1_TMR_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a2efd70def06239d90d9cfa77a554b478">XV_HDMIRX1_TMR2_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a3d6d8df87e3d66f70c7517431b791a10"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a3d6d8df87e3d66f70c7517431b791a10">XV_HDMIRX1_TMR_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR_CTRL_SET_OFFSET</div><div class="ttdoc">TMR Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:193</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a2efd70def06239d90d9cfa77a554b478"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a2efd70def06239d90d9cfa77a554b478">XV_HDMIRX1_TMR2_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR2_CTRL_RUN_MASK</div><div class="ttdoc">TMR Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:204</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
</div><!-- fragment -->
<p>This macro enables the HDMI RX timer peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a015741105c8cf02b20e69e03b65ccc71" title="This macro enables the HDMI RX timer peripheral. ">XV_HdmiRx1_Tmr2Enable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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          <td class="memname">#define XV_HdmiRx1_Tmr2IntrDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a1cdf2bc260e7b4039352ef7cea5638b9">XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ab49a117151e93626b4c4e6cfaa88fbca">XV_HDMIRX1_TMR2_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ab49a117151e93626b4c4e6cfaa88fbca"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ab49a117151e93626b4c4e6cfaa88fbca">XV_HDMIRX1_TMR2_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR2_CTRL_IE_MASK</div><div class="ttdoc">TMR Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:205</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a1cdf2bc260e7b4039352ef7cea5638b9"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a1cdf2bc260e7b4039352ef7cea5638b9">XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</div><div class="ttdoc">TMR Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:194</div></div>
</div><!-- fragment -->
<p>This macro disables interrupt in the HDMI RX timer peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#af026514eac245f4f7fea082361577997" title="This macro disables interrupt in the HDMI RX timer peripheral. ">XV_HdmiRx1_Tmr2IntrDisable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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          <td class="memname">#define XV_HdmiRx1_Tmr2IntrEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a3d6d8df87e3d66f70c7517431b791a10">XV_HDMIRX1_TMR_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ab49a117151e93626b4c4e6cfaa88fbca">XV_HDMIRX1_TMR2_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a3d6d8df87e3d66f70c7517431b791a10"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a3d6d8df87e3d66f70c7517431b791a10">XV_HDMIRX1_TMR_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR_CTRL_SET_OFFSET</div><div class="ttdoc">TMR Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:193</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ab49a117151e93626b4c4e6cfaa88fbca"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ab49a117151e93626b4c4e6cfaa88fbca">XV_HDMIRX1_TMR2_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR2_CTRL_IE_MASK</div><div class="ttdoc">TMR Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:205</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
</div><!-- fragment -->
<p>This macro enables interrupts in the HDMI RX timer peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#ac88f46543d066f90f95e6ca05e9561de" title="This macro enables interrupts in the HDMI RX timer peripheral. ">XV_HdmiRx1_Tmr2IntrEnable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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<a class="anchor" id="ab2b8c0c606b059fe056a78b9a93417b8"></a>
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          <td class="memname">#define XV_HdmiRx1_Tmr2Start</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Value&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#aeae47d24687bc43e32160a9308182746">XV_HDMIRX1_TMR2_CNT_OFFSET</a>), (u32)(Value))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_aeae47d24687bc43e32160a9308182746"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#aeae47d24687bc43e32160a9308182746">XV_HDMIRX1_TMR2_CNT_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR2_CNT_OFFSET</div><div class="ttdoc">TMR Counter Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:197</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
</div><!-- fragment -->
<p>This macro starts the HDMI RX timer peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#ab2b8c0c606b059fe056a78b9a93417b8" title="This macro starts the HDMI RX timer peripheral. ">XV_HdmiRx1_Tmr2Start(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#af10ef171597554725eb963e6ee83278b">XV_HdmiRx1_TmrStartMs()</a>.</p>

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          <td class="memname">#define XV_HdmiRx1_Tmr3Disable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a1cdf2bc260e7b4039352ef7cea5638b9">XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</a>),\</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#afeea10b36e6aae8f6924ff77a9f16989">XV_HDMIRX1_TMR3_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a1cdf2bc260e7b4039352ef7cea5638b9"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a1cdf2bc260e7b4039352ef7cea5638b9">XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</div><div class="ttdoc">TMR Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:194</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_afeea10b36e6aae8f6924ff77a9f16989"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#afeea10b36e6aae8f6924ff77a9f16989">XV_HDMIRX1_TMR3_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR3_CTRL_RUN_MASK</div><div class="ttdoc">TMR Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:206</div></div>
</div><!-- fragment -->
<p>This macro disables the HDMI RX timer peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#aadacbe89d70bbefbf1e71042d777ea92" title="This macro disables the HDMI RX timer peripheral. ">XV_HdmiRx1_Tmr3Disable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx1_8h.html#af7fd5d8f18778311dec6be080788f6f2">XV_HdmiRx1_Clear()</a>.</p>

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          <td class="memname">#define XV_HdmiRx1_Tmr3Enable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a3d6d8df87e3d66f70c7517431b791a10">XV_HDMIRX1_TMR_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#afeea10b36e6aae8f6924ff77a9f16989">XV_HDMIRX1_TMR3_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a3d6d8df87e3d66f70c7517431b791a10"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a3d6d8df87e3d66f70c7517431b791a10">XV_HDMIRX1_TMR_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR_CTRL_SET_OFFSET</div><div class="ttdoc">TMR Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:193</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_afeea10b36e6aae8f6924ff77a9f16989"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#afeea10b36e6aae8f6924ff77a9f16989">XV_HDMIRX1_TMR3_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR3_CTRL_RUN_MASK</div><div class="ttdoc">TMR Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:206</div></div>
</div><!-- fragment -->
<p>This macro enables the HDMI RX timer peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a7a1da40034b17fcdd3a0b4e62d17cf78" title="This macro enables the HDMI RX timer peripheral. ">XV_HdmiRx1_Tmr3Enable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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<a class="anchor" id="a963af2bc8daca1f5f771b75e7ed0f83d"></a>
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          <td class="memname">#define XV_HdmiRx1_Tmr3IntrDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a1cdf2bc260e7b4039352ef7cea5638b9">XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#aa49f4509e6046355bfdd463e060bf81d">XV_HDMIRX1_TMR3_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_aa49f4509e6046355bfdd463e060bf81d"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#aa49f4509e6046355bfdd463e060bf81d">XV_HDMIRX1_TMR3_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR3_CTRL_IE_MASK</div><div class="ttdoc">TMR Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:207</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a1cdf2bc260e7b4039352ef7cea5638b9"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a1cdf2bc260e7b4039352ef7cea5638b9">XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</div><div class="ttdoc">TMR Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:194</div></div>
</div><!-- fragment -->
<p>This macro disables interrupt in the HDMI RX timer peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a963af2bc8daca1f5f771b75e7ed0f83d" title="This macro disables interrupt in the HDMI RX timer peripheral. ">XV_HdmiRx1_Tmr3IntrDisable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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          <td class="memname">#define XV_HdmiRx1_Tmr3IntrEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a3d6d8df87e3d66f70c7517431b791a10">XV_HDMIRX1_TMR_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#aa49f4509e6046355bfdd463e060bf81d">XV_HDMIRX1_TMR3_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a3d6d8df87e3d66f70c7517431b791a10"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a3d6d8df87e3d66f70c7517431b791a10">XV_HDMIRX1_TMR_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR_CTRL_SET_OFFSET</div><div class="ttdoc">TMR Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:193</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_aa49f4509e6046355bfdd463e060bf81d"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#aa49f4509e6046355bfdd463e060bf81d">XV_HDMIRX1_TMR3_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR3_CTRL_IE_MASK</div><div class="ttdoc">TMR Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:207</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
</div><!-- fragment -->
<p>This macro enables interrupts in the HDMI RX timer peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a826103168347fef524be56f819b48b2d" title="This macro enables interrupts in the HDMI RX timer peripheral. ">XV_HdmiRx1_Tmr3IntrEnable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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<a class="anchor" id="a0b54de6bbd95ea2f25998c28db0fef69"></a>
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          <td class="memname">#define XV_HdmiRx1_Tmr3Start</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Value&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ae3314caa4470dc986d1d7a50f1de62c9">XV_HDMIRX1_TMR3_CNT_OFFSET</a>), (u32)(Value))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ae3314caa4470dc986d1d7a50f1de62c9"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ae3314caa4470dc986d1d7a50f1de62c9">XV_HDMIRX1_TMR3_CNT_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR3_CNT_OFFSET</div><div class="ttdoc">TMR Counter Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:198</div></div>
</div><!-- fragment -->
<p>This macro starts the HDMI RX timer peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a0b54de6bbd95ea2f25998c28db0fef69" title="This macro starts the HDMI RX timer peripheral. ">XV_HdmiRx1_Tmr3Start(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#af10ef171597554725eb963e6ee83278b">XV_HdmiRx1_TmrStartMs()</a>.</p>

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          <td class="memname">#define XV_HdmiRx1_Tmr4Disable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a1cdf2bc260e7b4039352ef7cea5638b9">XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</a>),\</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a404594f6834c97a323eccb1f6acf10e4">XV_HDMIRX1_TMR4_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a404594f6834c97a323eccb1f6acf10e4"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a404594f6834c97a323eccb1f6acf10e4">XV_HDMIRX1_TMR4_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR4_CTRL_RUN_MASK</div><div class="ttdoc">TMR Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:208</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a1cdf2bc260e7b4039352ef7cea5638b9"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a1cdf2bc260e7b4039352ef7cea5638b9">XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</div><div class="ttdoc">TMR Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:194</div></div>
</div><!-- fragment -->
<p>This macro disables the HDMI RX timer peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a1bbae2cd92459ab09caba931c2eeb766" title="This macro disables the HDMI RX timer peripheral. ">XV_HdmiRx1_Tmr4Disable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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<a class="anchor" id="ab3f9e1b5c62459aca4117b574e97cb20"></a>
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          <td class="memname">#define XV_HdmiRx1_Tmr4Enable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a3d6d8df87e3d66f70c7517431b791a10">XV_HDMIRX1_TMR_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a404594f6834c97a323eccb1f6acf10e4">XV_HDMIRX1_TMR4_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a404594f6834c97a323eccb1f6acf10e4"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a404594f6834c97a323eccb1f6acf10e4">XV_HDMIRX1_TMR4_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR4_CTRL_RUN_MASK</div><div class="ttdoc">TMR Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:208</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a3d6d8df87e3d66f70c7517431b791a10"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a3d6d8df87e3d66f70c7517431b791a10">XV_HDMIRX1_TMR_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR_CTRL_SET_OFFSET</div><div class="ttdoc">TMR Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:193</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
</div><!-- fragment -->
<p>This macro enables the HDMI RX timer peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#ab3f9e1b5c62459aca4117b574e97cb20" title="This macro enables the HDMI RX timer peripheral. ">XV_HdmiRx1_Tmr4Enable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_Tmr4IntrDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a1cdf2bc260e7b4039352ef7cea5638b9">XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ad4ccd558833c924e452e41b04f4aad67">XV_HDMIRX1_TMR4_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ad4ccd558833c924e452e41b04f4aad67"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ad4ccd558833c924e452e41b04f4aad67">XV_HDMIRX1_TMR4_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR4_CTRL_IE_MASK</div><div class="ttdoc">TMR Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:209</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a1cdf2bc260e7b4039352ef7cea5638b9"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a1cdf2bc260e7b4039352ef7cea5638b9">XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</div><div class="ttdoc">TMR Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:194</div></div>
</div><!-- fragment -->
<p>This macro disables interrupt in the HDMI RX timer peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a142ca05b75d070d95c61004b82bb5a68" title="This macro disables interrupt in the HDMI RX timer peripheral. ">XV_HdmiRx1_Tmr4IntrDisable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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<a class="anchor" id="a62815abff227bdf3168089698b368a9b"></a>
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          <td class="memname">#define XV_HdmiRx1_Tmr4IntrEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a3d6d8df87e3d66f70c7517431b791a10">XV_HDMIRX1_TMR_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ad4ccd558833c924e452e41b04f4aad67">XV_HDMIRX1_TMR4_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a3d6d8df87e3d66f70c7517431b791a10"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a3d6d8df87e3d66f70c7517431b791a10">XV_HDMIRX1_TMR_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR_CTRL_SET_OFFSET</div><div class="ttdoc">TMR Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:193</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ad4ccd558833c924e452e41b04f4aad67"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ad4ccd558833c924e452e41b04f4aad67">XV_HDMIRX1_TMR4_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR4_CTRL_IE_MASK</div><div class="ttdoc">TMR Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:209</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
</div><!-- fragment -->
<p>This macro enables interrupts in the HDMI RX timer peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a62815abff227bdf3168089698b368a9b" title="This macro enables interrupts in the HDMI RX timer peripheral. ">XV_HdmiRx1_Tmr4IntrEnable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_Tmr4Start</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Value&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a2b45e7f59deb365e580565110ec1be4e">XV_HDMIRX1_TMR4_CNT_OFFSET</a>), (u32)(Value))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a2b45e7f59deb365e580565110ec1be4e"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a2b45e7f59deb365e580565110ec1be4e">XV_HDMIRX1_TMR4_CNT_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_TMR4_CNT_OFFSET</div><div class="ttdoc">TMR Counter Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:199</div></div>
</div><!-- fragment -->
<p>This macro starts the HDMI RX timer peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a4de4494c309d24995f84a567459d7b31" title="This macro starts the HDMI RX timer peripheral. ">XV_HdmiRx1_Tmr4Start(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#af10ef171597554725eb963e6ee83278b">XV_HdmiRx1_TmrStartMs()</a>.</p>

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          <td class="memname">#define XV_HdmiRx1_VideoEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">SetClr&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (SetClr) { <a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">		XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#a519c487569199868a3cb9e63ca31c741">XV_HDMIRX1_PIO_OUT_VID_EN_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">        else { <a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">		XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#a519c487569199868a3cb9e63ca31c741">XV_HDMIRX1_PIO_OUT_VID_EN_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a9f3ee5ffefea5fea81b6278347ac0911"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_CLR_OFFSET</div><div class="ttdoc">PIO Out Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:92</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a519c487569199868a3cb9e63ca31c741"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a519c487569199868a3cb9e63ca31c741">XV_HDMIRX1_PIO_OUT_VID_EN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_VID_EN_MASK</div><div class="ttdoc">PIO Out video enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:114</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ada35683dde8266cadc45f975707d577b"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_PIO_OUT_SET_OFFSET</div><div class="ttdoc">PIO Out Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:91</div></div>
</div><!-- fragment -->
<p>This macro asserts or clears the HDMI RX video enable. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance. </td></tr>
    <tr><td class="paramname">SetClr</td><td>specifies TRUE/FALSE value to either assert or release HDMI RX video enable.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a33e7dd96086ade48b9cf40729dc5e997" title="This macro asserts or clears the HDMI RX reset. ">XV_HdmiRx1_Reset(XV_HdmiRx1 *InstancePtr, u8 SetClr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiRx1_VtdDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ae971e94da9cfb5a7a9b682ae3526bb44">XV_HDMIRX1_VTD_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ad3255aafdf1db8869d62b1ab51d58ad0">XV_HDMIRX1_VTD_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ae971e94da9cfb5a7a9b682ae3526bb44"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ae971e94da9cfb5a7a9b682ae3526bb44">XV_HDMIRX1_VTD_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_VTD_CTRL_CLR_OFFSET</div><div class="ttdoc">VTD Control Clear Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:223</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ad3255aafdf1db8869d62b1ab51d58ad0"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ad3255aafdf1db8869d62b1ab51d58ad0">XV_HDMIRX1_VTD_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_VTD_CTRL_RUN_MASK</div><div class="ttdoc">VTD Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:237</div></div>
</div><!-- fragment -->
<p>This macro disables the HDMI RX Timing Detector peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#ab5508950e173aa4b8c4736e0ae09266c" title="This macro disables the HDMI RX Timing Detector peripheral. ">XV_HdmiRx1_VtdDisable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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<a class="anchor" id="a1ef161f38b2d9108a4923fec0fc880f1"></a>
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          <td class="memname">#define XV_HdmiRx1_VtdEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a373df61175a1b81c8c49973a7c429c8a">XV_HDMIRX1_VTD_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ad3255aafdf1db8869d62b1ab51d58ad0">XV_HDMIRX1_VTD_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a373df61175a1b81c8c49973a7c429c8a"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a373df61175a1b81c8c49973a7c429c8a">XV_HDMIRX1_VTD_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_VTD_CTRL_SET_OFFSET</div><div class="ttdoc">VTD Control Set Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:222</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ad3255aafdf1db8869d62b1ab51d58ad0"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ad3255aafdf1db8869d62b1ab51d58ad0">XV_HDMIRX1_VTD_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_VTD_CTRL_RUN_MASK</div><div class="ttdoc">VTD Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:237</div></div>
</div><!-- fragment -->
<p>This macro enables the HDMI RX Timing Detector peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a1ef161f38b2d9108a4923fec0fc880f1" title="This macro enables the HDMI RX Timing Detector peripheral. ">XV_HdmiRx1_VtdEnable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="a59b4dbbffb9eeec8b22acc012d22e07f"></a>
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          <td class="memname">#define XV_HdmiRx1_VtdIntrDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#ae971e94da9cfb5a7a9b682ae3526bb44">XV_HDMIRX1_VTD_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a778b05c24de8ad264eb1fe2cc33e88af">XV_HDMIRX1_VTD_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ae971e94da9cfb5a7a9b682ae3526bb44"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ae971e94da9cfb5a7a9b682ae3526bb44">XV_HDMIRX1_VTD_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_VTD_CTRL_CLR_OFFSET</div><div class="ttdoc">VTD Control Clear Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:223</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a778b05c24de8ad264eb1fe2cc33e88af"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a778b05c24de8ad264eb1fe2cc33e88af">XV_HDMIRX1_VTD_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_VTD_CTRL_IE_MASK</div><div class="ttdoc">VTD Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:238</div></div>
</div><!-- fragment -->
<p>This macro disables interrupt in the HDMI RX Timing Detector peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a59b4dbbffb9eeec8b22acc012d22e07f" title="This macro disables interrupt in the HDMI RX Timing Detector peripheral. ">XV_HdmiRx1_VtdIntrDisable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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<a class="anchor" id="af02bc319e791bee6ef832346327dd0be"></a>
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          <td class="memname">#define XV_HdmiRx1_VtdIntrEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
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<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a373df61175a1b81c8c49973a7c429c8a">XV_HDMIRX1_VTD_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a778b05c24de8ad264eb1fe2cc33e88af">XV_HDMIRX1_VTD_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a373df61175a1b81c8c49973a7c429c8a"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a373df61175a1b81c8c49973a7c429c8a">XV_HDMIRX1_VTD_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_VTD_CTRL_SET_OFFSET</div><div class="ttdoc">VTD Control Set Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:222</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a778b05c24de8ad264eb1fe2cc33e88af"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a778b05c24de8ad264eb1fe2cc33e88af">XV_HDMIRX1_VTD_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_VTD_CTRL_IE_MASK</div><div class="ttdoc">VTD Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:238</div></div>
</div><!-- fragment -->
<p>This macro enables interrupt in the HDMI RX Timing Detector peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#af02bc319e791bee6ef832346327dd0be" title="This macro enables interrupt in the HDMI RX Timing Detector peripheral. ">XV_HdmiRx1_VtdIntrEnable(XV_HdmiRx1 *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="a56b0470904fc7dad8850ce0b88738404"></a>
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          <td class="memname">#define XV_HdmiRx1_VtdSetTimebase</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Value&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmirx1__hw_8h.html#a38f34bcb7e8f5d9de99c03aacd27353b">XV_HDMIRX1_VTD_CTRL_OFFSET</a>), \</div>
<div class="line">                            (u32)(Value &lt;&lt; <a class="code" href="xv__hdmirx1__hw_8h.html#aceaecabf406db886ed55dfe8f36abddc">XV_HDMIRX1_VTD_CTRL_TIMEBASE_SHIFT</a>))</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_aceaecabf406db886ed55dfe8f36abddc"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#aceaecabf406db886ed55dfe8f36abddc">XV_HDMIRX1_VTD_CTRL_TIMEBASE_SHIFT</a></div><div class="ttdeci">#define XV_HDMIRX1_VTD_CTRL_TIMEBASE_SHIFT</div><div class="ttdoc">VTD Control timebase shift. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:242</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a38f34bcb7e8f5d9de99c03aacd27353b"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a38f34bcb7e8f5d9de99c03aacd27353b">XV_HDMIRX1_VTD_CTRL_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_VTD_CTRL_OFFSET</div><div class="ttdoc">VTD Control Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:221</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
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<p>This macro sets the timebase in the HDMI RX Timing Detector peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a56b0470904fc7dad8850ce0b88738404" title="This macro sets the timebase in the HDMI RX Timing Detector peripheral. ">XV_HdmiRx1_VtdSetTimebase(XV_HdmiRx1 *InstancePtr, Value)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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<a class="anchor" id="a922e50f2b67a8bb2db9ed7eda0e8e347"></a>
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          <td class="memname">#define XV_HdmiRx1_VtdVfpEvent</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">SetClr&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (SetClr) { <a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">		XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#a373df61175a1b81c8c49973a7c429c8a">XV_HDMIRX1_VTD_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#a0d60962ac4dd676e0835f784cb4fa8b3">XV_HDMIRX1_VTD_CTRL_VFP_ENABLE_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">        else { <a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">\</a></div>
<div class="line"><a class="code" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">		XV_HdmiRx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#ae971e94da9cfb5a7a9b682ae3526bb44">XV_HDMIRX1_VTD_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmirx1__hw_8h.html#a0d60962ac4dd676e0835f784cb4fa8b3">XV_HDMIRX1_VTD_CTRL_VFP_ENABLE_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a373df61175a1b81c8c49973a7c429c8a"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a373df61175a1b81c8c49973a7c429c8a">XV_HDMIRX1_VTD_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_VTD_CTRL_SET_OFFSET</div><div class="ttdoc">VTD Control Set Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:222</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a0d60962ac4dd676e0835f784cb4fa8b3"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a0d60962ac4dd676e0835f784cb4fa8b3">XV_HDMIRX1_VTD_CTRL_VFP_ENABLE_MASK</a></div><div class="ttdeci">#define XV_HDMIRX1_VTD_CTRL_VFP_ENABLE_MASK</div><div class="ttdoc">VTD VFP change interrupt enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:241</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_ae971e94da9cfb5a7a9b682ae3526bb44"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#ae971e94da9cfb5a7a9b682ae3526bb44">XV_HDMIRX1_VTD_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMIRX1_VTD_CTRL_CLR_OFFSET</div><div class="ttdoc">VTD Control Clear Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:223</div></div>
<div class="ttc" id="xv__hdmirx1__hw_8h_html_a949523423dffb540041a98a38e283cf8"><div class="ttname"><a href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiRx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI RX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmirx1_hw.h:804</div></div>
</div><!-- fragment -->
<p>This macro allow control to enable/disable the HDMI RX VFP event. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance. </td></tr>
    <tr><td class="paramname">SetClr</td><td>specifies TRUE/FALSE value to either enable or disable the VFP Event</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a922e50f2b67a8bb2db9ed7eda0e8e347" title="This macro allow control to enable/disable the HDMI RX VFP event. ">XV_HdmiRx1_VtdVfpEvent(XV_HdmiRx1 *InstancePtr, u8 SetClr)</a> </dd></dl>

</div>
</div>
<h2 class="groupheader">Typedef Documentation</h2>
<a class="anchor" id="a57932e2a1e2c690514833984d086b096"></a>
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          <td class="memname">typedef void(* XV_HdmiRx1_Callback)(void *CallbackRef)</td>
        </tr>
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<p>Callback type for interrupt. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">CallbackRef</td><td>is a callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

</div>
</div>
<h2 class="groupheader">Enumeration Type Documentation</h2>
<a class="anchor" id="abbfb262ec57764dd666d070dbda26942"></a>
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          <td class="memname">enum <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942">XV_HdmiRx1_HandlerType</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>These constants specify different types of handler and used to differentiate interrupt requests from peripheral. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942a9b4c4aa468273738a419e39c05f0baad"></a>XV_HDMIRX1_HANDLER_CONNECT</em>&nbsp;</td><td class="fielddoc">
<p>A connect event interrupt type. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942aebb0160b6b43a4f4e859f45e017faa34"></a>XV_HDMIRX1_HANDLER_BRDG_OVERFLOW</em>&nbsp;</td><td class="fielddoc">
<p>Interrupt type for bridge verflow. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942adc98639f1c812cd5a2a72f8cac74c868"></a>XV_HDMIRX1_HANDLER_AUX</em>&nbsp;</td><td class="fielddoc">
<p>Interrupt type for AUX peripheral. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942aa481e1b0c381c69e68f4a336c4f4291a"></a>XV_HDMIRX1_HANDLER_AUD</em>&nbsp;</td><td class="fielddoc">
<p>Interrupt type for AUD peripheral. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942a7a01589f01cadd752b2d205f643756b8"></a>XV_HDMIRX1_HANDLER_LNKSTA</em>&nbsp;</td><td class="fielddoc">
<p>Interrupt type for LNKSTA peripheral. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942aff8d61798f42199bedb5c4ccce598ff2"></a>XV_HDMIRX1_HANDLER_DDC</em>&nbsp;</td><td class="fielddoc">
<p>Interrupt type for DDC peripheral. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942a0433f28ecdfbbaa25be35be1a1864320"></a>XV_HDMIRX1_HANDLER_STREAM_DOWN</em>&nbsp;</td><td class="fielddoc">
<p>Interrupt type for stream down. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942a4759661b3e3b5ec737b4f42194e1c102"></a>XV_HDMIRX1_HANDLER_STREAM_INIT</em>&nbsp;</td><td class="fielddoc">
<p>Interrupt type for stream init. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942a79eb6929b21502e375b3621268df1ead"></a>XV_HDMIRX1_HANDLER_STREAM_UP</em>&nbsp;</td><td class="fielddoc">
<p>Interrupt type for stream up. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942a712a8fe2d8cbaa4d6f30a9a34844f1d9"></a>XV_HDMIRX1_HANDLER_HDCP</em>&nbsp;</td><td class="fielddoc">
<p>Interrupt type for hdcp. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942aa0db97ee67a4f31597b3418b6e988338"></a>XV_HDMIRX1_HANDLER_DDC_HDCP_14_PROT</em>&nbsp;</td><td class="fielddoc">
<p>Interrupt type for HDCP14PROT event. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942aa9498efdb463dd326e02e578db4e6871"></a>XV_HDMIRX1_HANDLER_DDC_HDCP_22_PROT</em>&nbsp;</td><td class="fielddoc">
<p>Interrupt type for HDCP22PROT event. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942a39fd4542c7878df53d3bf3d18d6762a2"></a>XV_HDMIRX1_HANDLER_LINK_ERROR</em>&nbsp;</td><td class="fielddoc">
<p>Interrupt type for link error. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942af9cf2bdb04e25e90100885f80be68d12"></a>XV_HDMIRX1_HANDLER_SYNC_LOSS</em>&nbsp;</td><td class="fielddoc">
<p>Interrupt type for sync loss. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942ae118085eb55b228455f78663cb661a27"></a>XV_HDMIRX1_HANDLER_MODE</em>&nbsp;</td><td class="fielddoc">
<p>Interrupt type for mode. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942a2c3b39213e1ef49751a14777963398d5"></a>XV_HDMIRX1_HANDLER_TMDS_CLK_RATIO</em>&nbsp;</td><td class="fielddoc">
<p>Interrupt type for TMDS clock ratio. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942a314a6cd00e81397687bdda8b4f073768"></a>XV_HDMIRX1_HANDLER_VIC_ERROR</em>&nbsp;</td><td class="fielddoc">
<p>Interrupt type for VIC error. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942a6ab6e9177942ae3f4bd6ed8bfa5873b6"></a>XV_HDMIRX1_HANDLER_PHY_RESET</em>&nbsp;</td><td class="fielddoc">
<p>Handler for Configuration Retry Request. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942a03722585c04e5e62c80b912854856f31"></a>XV_HDMIRX1_HANDLER_LNK_RDY_ERR</em>&nbsp;</td><td class="fielddoc">
<p>Interrupt type for Link Ready error. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942a73d3498284bf4989a39e48a55146abf3"></a>XV_HDMIRX1_HANDLER_VID_RDY_ERR</em>&nbsp;</td><td class="fielddoc">
<p>Interrupt type for Video Ready error. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942a9f4c993efb8541e185ba312968e89d93"></a>XV_HDMIRX1_HANDLER_SKEW_LOCK_ERR</em>&nbsp;</td><td class="fielddoc">
<p>Interrupt type for Skew Lock error. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942aff9bf32f7a33b804800d8d5706986fd9"></a>XV_HDMIRX1_HANDLER_FRL_CONFIG</em>&nbsp;</td><td class="fielddoc">
<p>Handler for FRL Config. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942ab0d40648a4270a90b8816085080c2dc4"></a>XV_HDMIRX1_HANDLER_FRL_START</em>&nbsp;</td><td class="fielddoc">
<p>Handler for FRL Start. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942a19d8897bb48beef6cc192dce8e656224"></a>XV_HDMIRX1_HANDLER_TMDS_CONFIG</em>&nbsp;</td><td class="fielddoc">
<p>Handler for TMDS. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942a9b60139f3a0336b0e920ab5dd18dc183"></a>XV_HDMIRX1_HANDLER_VFP_CHANGE</em>&nbsp;</td><td class="fielddoc">
<p>Handler for VFP change event. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942a19a71662e67c08479b6f24a6c6930be7"></a>XV_HDMIRX1_HANDLER_VRR_RDY</em>&nbsp;</td><td class="fielddoc">
<p>Handler for VRR rdy event. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942a6c6dec8c2000bd56980e104718de20b8"></a>XV_HDMIRX1_HANDLER_DYN_HDR</em>&nbsp;</td><td class="fielddoc">
<p>Handler for Dynamic HDR. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942ae440e854baa6be9065fa24b541a211a8"></a>XV_HDMIRX1_HANDLER_DSC_STRM_CH</em>&nbsp;</td><td class="fielddoc">
<p>Handler type for DSC stream change event. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942abd439ec152f3be928e4b1a78f6e462f8"></a>XV_HDMIRX1_HANDLER_DSC_PKT_ERR</em>&nbsp;</td><td class="fielddoc">
<p>Handler type for DSC PPS Packet error event. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="abbfb262ec57764dd666d070dbda26942a7e57e5a185607118363c0a8d86b20c6d"></a>XV_HDMIRX1_HANDLER_DSC_STS_UPDT</em>&nbsp;</td><td class="fielddoc">
<p>Handler type for SCDC Reg 0x10 bit 0 Status_Update bit set by HDMI Source. </p>
</td></tr>
</table>

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          <td class="memname">enum <a class="el" href="xv__hdmirx1_8h.html#aaff80d21f94c4b494ab6beb909f74eba">XV_HdmiRx1_State</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="aaff80d21f94c4b494ab6beb909f74ebaa9b3b6fc66356c86b1e37dc20b4a69933"></a>XV_HDMIRX1_STATE_STREAM_DOWN</em>&nbsp;</td><td class="fielddoc">
<p>Stream down. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="aaff80d21f94c4b494ab6beb909f74ebaaa1f34d784d248ada4547ce9c98d6fb0c"></a>XV_HDMIRX1_STATE_STREAM_IDLE</em>&nbsp;</td><td class="fielddoc">
<p>Stream idle. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="aaff80d21f94c4b494ab6beb909f74ebaa951d06813050d87c5939cfaaced6e8df"></a>XV_HDMIRX1_STATE_STREAM_INIT</em>&nbsp;</td><td class="fielddoc">
<p>Stream init. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="aaff80d21f94c4b494ab6beb909f74ebaa9809e0d6666c90f18ac68d18aa56f46f"></a>XV_HDMIRX1_STATE_STREAM_ARM</em>&nbsp;</td><td class="fielddoc">
<p>Stream arm. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="aaff80d21f94c4b494ab6beb909f74ebaad8dee1d15d52d9c72cb69452261e3104"></a>XV_HDMIRX1_STATE_STREAM_LOCK</em>&nbsp;</td><td class="fielddoc">
<p>Stream lock. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="aaff80d21f94c4b494ab6beb909f74ebaa68f8ec479e8bdfc98649a9bfde2405a7"></a>XV_HDMIRX1_STATE_STREAM_RDY</em>&nbsp;</td><td class="fielddoc">
<p>Stream ready. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="aaff80d21f94c4b494ab6beb909f74ebaa78cc6e34272e81a858d62f92557a3950"></a>XV_HDMIRX1_STATE_STREAM_UP</em>&nbsp;</td><td class="fielddoc">
<p>Stream up. </p>
</td></tr>
</table>

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<div class="memproto">
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        <tr>
          <td class="memname">enum <a class="el" href="xv__hdmirx1_8h.html#a78b0c5167ed122389fed2d59f379a775">XV_HdmiRx1_SyncStatus</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="a78b0c5167ed122389fed2d59f379a775a01cffeb117a47b14208e30c8dd82ee24"></a>XV_HDMIRX1_SYNCSTAT_SYNC_LOSS</em>&nbsp;</td><td class="fielddoc">
<p>Sync Loss. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="a78b0c5167ed122389fed2d59f379a775a2f310f02db1fab96adfecbb7d4a47070"></a>XV_HDMIRX1_SYNCSTAT_SYNC_EST</em>&nbsp;</td><td class="fielddoc">
<p>Sync Lock. </p>
</td></tr>
</table>

</div>
</div>
<h2 class="groupheader">Function Documentation</h2>
<a class="anchor" id="ae8f2b92316ba8599c678aa9168d2eb24"></a>
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          <td class="memname">int XV_HdmiRx1_CfgInitialize </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1___config.html">XV_HdmiRx1_Config</a> *&#160;</td>
          <td class="paramname"><em>CfgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>EffectiveAddr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function initializes the HDMI RX core. </p>
<p>This function must be called prior to using the HDMI RX core. Initialization of the HDMI RX includes setting up the instance data, and ensuring the hardware is in a quiescent state.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmiRx1 core instance. </td></tr>
    <tr><td class="paramname">CfgPtr</td><td>points to the configuration structure associated with the HDMI RX core. </td></tr>
    <tr><td class="paramname">EffectiveAddr</td><td>is the base address of the device. If address translation is being used, then this parameter must reflect the virtual base address. Otherwise, the physical address should be used.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if XV_HdmiRx1_CfgInitialize was successful.</li>
<li>XST_FAILURE if HDMI RX PIO ID mismatched.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1.html#ac6cde43853e1f68b75e12786b8b27184">XV_HdmiRx1::AudCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a03b60e69b1ded28e64fc01497d9ea02c">XV_HdmiRx1::AuxCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ab71556ccd55ddd82fd84890c4e09df18">XV_HdmiRx1::ConnectCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1___frl.html#af43d413c9a668400e3c0b8fbac302e19">XV_HdmiRx1_Frl::CurFrlRate</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#af1a889495687e670d6a591170761a810">XV_HdmiRx1::DdcCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1___frl.html#a0f554039b7fe90c629cb245a727540b7">XV_HdmiRx1_Frl::DefaultLtp</a>, <a class="el" href="struct_x_v___hdmi_rx1___config.html#ac0ebea46345e62a86c591fa7b7630e18">XV_HdmiRx1_Config::DSC</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ad3c15f528662fba6efbc2bf5a1d034a0">XV_HdmiRx1::FrlConfigCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a287b6bb5e1ca228324f5126907f03a6c">XV_HdmiRx1::FrlStartCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a332b700f16b8e3826767971c3bf859b2">XV_HdmiRx1::HdcpCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ae0248f4981813e9e7d4556a02608a371">XV_HdmiRx1::HdcpRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a702c45e45b496ad8b6aa51238a8b5bb2">XV_HdmiRx1::IsReady</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a6389ceb5ffcc260ea4e14df3b8488d45">XV_HdmiRx1::LinkErrorCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a65bf83a0a4a7289ed9b2b4ce701ac8dd">XV_HdmiRx1::LnkStaCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aee0b055b6e7208d61012abdae2df5018">XV_HdmiRx1::ModeCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#adf8543d358aeaf359d915412003845e3">XV_HdmiRx1::Stream</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a4e92779a4947b7ff5ec5ea6fe0c0417c">XV_HdmiRx1::StreamDownCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ae72087cc837d809b1beaa9d8b798c9db">XV_HdmiRx1::StreamInitCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a54c1ff6cbf1c7d1c8a7e0323e60d64b6">XV_HdmiRx1::StreamUpCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a81e87ae653cb737329383942f3d51df5">XV_HdmiRx1::SyncLossCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a2838b98abee66bedb928f74f015fd40e">XV_HdmiRx1::TmdsClkRatioCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ae6f5c0eabdc405e9ee6cbfd455873587">XV_HdmiRx1::TmdsConfigCallback</a>, <a class="el" href="xv__hdmirx1_8h.html#a4ddfdbb13a735158eac6316b10fe827b">XV_HdmiRx1_AudioDisable</a>, <a class="el" href="xv__hdmirx1_8h.html#a48cc569dd4043d7d85a22e18f3e7ff14">XV_HdmiRx1_AudioIntrEnable</a>, <a class="el" href="xv__hdmirx1_8h.html#ab7b551cd29147914edb614a75ad72106">XV_HdmiRx1_AuxDisable</a>, <a class="el" href="xv__hdmirx1_8h.html#a167821ef9d8c222d4d8c1bc194e1d42b">XV_HdmiRx1_AuxFSyncVrrChEvtEnable</a>, <a class="el" href="xv__hdmirx1_8h.html#af5e8e60bd7c915758d1a6961901427cc">XV_HdmiRx1_AuxIntrEnable</a>, <a class="el" href="xv__hdmirx1_8c.html#af7fd5d8f18778311dec6be080788f6f2">XV_HdmiRx1_Clear()</a>, <a class="el" href="xv__hdmirx1_8h.html#afa5c7f669b19e1b0f9cbad39adb674bc">XV_HdmiRx1_DdcDisable</a>, <a class="el" href="xv__hdmirx1_8h.html#a2fa160f04e804a5214822c2031bcce4a">XV_HdmiRx1_DdcEnable</a>, <a class="el" href="xv__hdmirx1_8h.html#ad2801bbba5e4a3492373d59f783bc0b4">XV_HdmiRx1_DdcScdcClear</a>, <a class="el" href="xv__hdmirx1_8h.html#a29847cccb96616c7a70252a0ae823e67">XV_HdmiRx1_DdcScdcEnable</a>, <a class="el" href="xv__hdmirx1_8h.html#ab17e4f96ebbe6785b411233165de859a">XV_HdmiRx1_FrlDdcWriteField()</a>, <a class="el" href="xv__hdmirx1_8h.html#a04b941fdfc281d7d81665d47ac32f1d2">XV_HdmiRx1_FrlReset()</a>, <a class="el" href="xv__hdmirx1_8h.html#ab5713966b53828111f26a3a75e0e8d1a">XV_HdmiRx1_GetTime16Ms</a>, <a class="el" href="xv__hdmirx1_8h.html#ad50e1b7607576055e893d5b671ab20e8">XV_HdmiRx1_LnkstaDisable</a>, <a class="el" href="xv__hdmirx1_8h.html#a82a49f48613a311ebd77b7c06d774287">XV_HdmiRx1_LnkstaEnable</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a090582e52a472f924918d70505f62b11">XV_HDMIRX1_MASK_16</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa303f116af14392fe13aebd0cc78a125">XV_HDMIRX1_PIO_ID</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#af194c444b1a273aed3950eca10ca1135">XV_HDMIRX1_PIO_ID_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a04e11b499092095ce68d48fc3f40e04c">XV_HDMIRX1_PIO_IN_BRDG_OVERFLOW_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a106ccba962224187a330b068ddd772c1">XV_HDMIRX1_PIO_IN_DET_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a5223536dada6b7c9610aea11ae7a190b">XV_HDMIRX1_PIO_IN_DSC_EN_STRM_CHG_EVT_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ad9a3ed590d3044b9978cdcd1a20abe06">XV_HDMIRX1_PIO_IN_DSC_PPS_PKT_ERR_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a84f86b84d6ad904b4c48821aacd45533">XV_HDMIRX1_PIO_IN_EVT_FE_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a0560f28ec4c56a00c8922c127fabcbee">XV_HDMIRX1_PIO_IN_EVT_RE_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a4ac3277902c44edfcce1cc6c8afcf2e3">XV_HDMIRX1_PIO_IN_LNK_RDY_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a9e9029db2aff750b7c208c8eca7faff9">XV_HDMIRX1_PIO_IN_MODE_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ac0cdb812388d2c6c671cc5e884eed62f">XV_HDMIRX1_PIO_IN_SCDC_SCRAMBLER_ENABLE_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a51d2852cd78f9a896e224454b97f092b">XV_HDMIRX1_PIO_IN_SCDC_TMDS_CLOCK_RATIO_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a7e39e0c95a43c2962ee66c1a45f3fbed">XV_HDMIRX1_PIO_IN_VID_RDY_MASK</a>, <a class="el" href="xv__hdmirx1_8h.html#a4d57a91b21377a43a2692f64564bc121">XV_HdmiRx1_PioDisable</a>, <a class="el" href="xv__hdmirx1_8h.html#ae5f391082b5e60a7ea25086124900070">XV_HdmiRx1_PioIntrDisable</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>, <a class="el" href="xv__hdmirx1_8h.html#a4806363b327ac1b624d0b470ab46c142">XV_HdmiRx1_SetFrlRateWrEvent_En()</a>, <a class="el" href="xv__hdmirx1_8c.html#ac7552beea455de7ac51452cb284241f3">XV_HdmiRx1_SetHpd()</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a44f9bde6a5097e3b1c287447e8292f87">XV_HDMIRX1_SHIFT_16</a>, <a class="el" href="xv__hdmirx1_8h.html#aec115cc3973ecedde65e4b11d3ad5b5b">XV_HdmiRx1_Tmr1Disable</a>, <a class="el" href="xv__hdmirx1_8h.html#a056971e8df07e73576859f1d25eb5b96">XV_HdmiRx1_Tmr1Enable</a>, <a class="el" href="xv__hdmirx1_8h.html#a267240b43d2cadda19be932109867557">XV_HdmiRx1_Tmr1IntrDisable</a>, <a class="el" href="xv__hdmirx1_8h.html#a27d61d0271f92f32b92971dcd726c2ca">XV_HdmiRx1_Tmr1IntrEnable</a>, <a class="el" href="xv__hdmirx1_8h.html#a1faa4df9824550b8f828d68597ddd2c1">XV_HdmiRx1_Tmr2Disable</a>, <a class="el" href="xv__hdmirx1_8h.html#a015741105c8cf02b20e69e03b65ccc71">XV_HdmiRx1_Tmr2Enable</a>, <a class="el" href="xv__hdmirx1_8h.html#af026514eac245f4f7fea082361577997">XV_HdmiRx1_Tmr2IntrDisable</a>, <a class="el" href="xv__hdmirx1_8h.html#ac88f46543d066f90f95e6ca05e9561de">XV_HdmiRx1_Tmr2IntrEnable</a>, <a class="el" href="xv__hdmirx1_8h.html#aadacbe89d70bbefbf1e71042d777ea92">XV_HdmiRx1_Tmr3Disable</a>, <a class="el" href="xv__hdmirx1_8h.html#a7a1da40034b17fcdd3a0b4e62d17cf78">XV_HdmiRx1_Tmr3Enable</a>, <a class="el" href="xv__hdmirx1_8h.html#a963af2bc8daca1f5f771b75e7ed0f83d">XV_HdmiRx1_Tmr3IntrDisable</a>, <a class="el" href="xv__hdmirx1_8h.html#a826103168347fef524be56f819b48b2d">XV_HdmiRx1_Tmr3IntrEnable</a>, <a class="el" href="xv__hdmirx1_8h.html#a1bbae2cd92459ab09caba931c2eeb766">XV_HdmiRx1_Tmr4Disable</a>, <a class="el" href="xv__hdmirx1_8h.html#a142ca05b75d070d95c61004b82bb5a68">XV_HdmiRx1_Tmr4IntrDisable</a>, <a class="el" href="xv__hdmirx1_8h.html#ab5508950e173aa4b8c4736e0ae09266c">XV_HdmiRx1_VtdDisable</a>, <a class="el" href="xv__hdmirx1_8h.html#a59b4dbbffb9eeec8b22acc012d22e07f">XV_HdmiRx1_VtdIntrDisable</a>, <a class="el" href="xv__hdmirx1_8h.html#a56b0470904fc7dad8850ce0b88738404">XV_HdmiRx1_VtdSetTimebase</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiRx1_Clear </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function clears the HDMI RX variables and sets them to the defaults. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This is required after a reset or init. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___audio_stream.html#a29818d1e0242ab44184ca5025858f41d">XV_HdmiRx1_AudioStream::Active</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a1f1d3dba8440eab1b16fa2e9bbdc63fa">XV_HdmiRx1::AudCts</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ad42e02b06b2c76ab3088ae992056cad6">XV_HdmiRx1::AudFormat</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a05571834a2194dd996c7c1638f6825c5">XV_HdmiRx1::AudN</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a48707022720d8ba22157d38026101285">XV_HdmiRx1::Aux</a>, <a class="el" href="struct_x_v___hdmi_rx1___audio_stream.html#a5913b7bda0855132f5bdbcb506fb543a">XV_HdmiRx1_AudioStream::Channels</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a59c722dfcd49130ef9a2fdddfbb84ce8">XV_HdmiRx1::IsErrorPrintCount</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#adf8543d358aeaf359d915412003845e3">XV_HdmiRx1::Stream</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a4e92779a4947b7ff5ec5ea6fe0c0417c">XV_HdmiRx1::StreamDownCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aca26516c2edc8f4444b8fd8e76cf708d">XV_HdmiRx1::StreamDownRef</a>, <a class="el" href="struct_x_v___hdmi_rx1___frl.html#a0eb1fb5490f5c6416d49455599444083">XV_HdmiRx1_Frl::TrainingState</a>, <a class="el" href="xv__hdmirx1_8h.html#aaff80d21f94c4b494ab6beb909f74ebaa9b3b6fc66356c86b1e37dc20b4a69933">XV_HDMIRX1_STATE_STREAM_DOWN</a>, and <a class="el" href="xv__hdmirx1_8h.html#aadacbe89d70bbefbf1e71042d777ea92">XV_HdmiRx1_Tmr3Disable</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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          <td class="memname">void XV_HdmiRx1_ClearLinkStatus </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function clears the link error counters. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a0ea4dac580c41d65c59984742c93fcaf">XV_HDMIRX1_LNKSTA_CTRL_CLR_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#adf40e22e8f2c99293f379a117807d84d">XV_HDMIRX1_LNKSTA_CTRL_ERR_CLR_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a23eec7113adc6c29ad2a46331582ae29">XV_HDMIRX1_LNKSTA_CTRL_SET_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

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          <td class="memname">int XV_HdmiRx1_ConfigFrlLtpDetection </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function configures the link training pattern to be detected. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Status<ul>
<li>XST_FAILURE<ul>
<li>Source has not cleared FLT_update so sink should not update FLT_req and FLT_update as to ensure proper data handshake</li>
<li>XST_SUCCESS</li>
<li>Source has cleared FLT_update and sink has updated LTP_req and set FLT_update to 1</li>
<li>XST_NO_DATA</li>
<li>Source has cleared FLT_update but no update from sink is required</li>
</ul>
</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="struct_x_v___hdmi_rx1___frl.html#af43d413c9a668400e3c0b8fbac302e19">XV_HdmiRx1_Frl::CurFrlRate</a>, <a class="el" href="struct_x_v___hdmi_rx1___frl.html#a0f554039b7fe90c629cb245a727540b7">XV_HdmiRx1_Frl::DefaultLtp</a>, <a class="el" href="struct_x_v___hdmi_rx1___frl.html#a21a4013614c2eae5fd14968ad790c669">XV_HdmiRx1_Frl::Ltp</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#adf8543d358aeaf359d915412003845e3">XV_HdmiRx1::Stream</a>, <a class="el" href="struct_x_v___hdmi_rx1___frl.html#a0eb1fb5490f5c6416d49455599444083">XV_HdmiRx1_Frl::TrainingState</a>, <a class="el" href="xv__hdmirx1_8h.html#a6010db11abd7d7a7b935d20b693c5b7a">XV_HdmiRx1_GetFrlLtpDetection()</a>, <a class="el" href="xv__hdmirx1_8h.html#a7de25fdf8166abb9ae7a4f9a3d7b5555">XV_HdmiRx1_GetTmr1Value</a>, <a class="el" href="xv__hdmirx1_8h.html#a0544f5226d2072e3a594677139f54d70">XV_HdmiRx1_ResetFrlLtpDetection()</a>, and <a class="el" href="xv__hdmirx1_8h.html#adf3222be232d5b0eaabeb5fbba4258fa">XV_HdmiRx1_SetFrlLtpDetection()</a>.</p>

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          <td class="memname">u16 XV_HdmiRx1_DdcGetHdcpReadMessageBufferWords </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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      </table>
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<p>This function gets the number of bytes of the HDCP 2.2 read buffer in the DDC slave. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Rx core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>HDCP 2.2 read buffer words</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa2e6b62c7b7e30d408bd3743409310f9">XV_HDMIRX1_DDC_HDCP_STA_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aee72508c9844747a42defa2b3f2ce8dc">XV_HDMIRX1_DDC_STA_HDCP_RMSG_WORDS_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a10fc375c829dc41f2417ba5f3ebc2fe5">XV_HDMIRX1_DDC_STA_HDCP_RMSG_WORDS_SHIFT</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>.</p>

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          <td class="memname">u16 XV_HdmiRx1_DdcGetHdcpWriteMessageBufferWords </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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      </table>
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<p>This function gets the number of bytes of the HDCP 2.2 write buffer in the DDC slave. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Rx core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>HDCP 2.2 write buffer words</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa2e6b62c7b7e30d408bd3743409310f9">XV_HDMIRX1_DDC_HDCP_STA_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a5adb107c4de97c736e7e7ab634212474">XV_HDMIRX1_DDC_STA_HDCP_WMSG_WORDS_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ab61a6b938d6e9f9579506c97512c7729">XV_HDMIRX1_DDC_STA_HDCP_WMSG_WORDS_SHIFT</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>.</p>

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          <td class="memname">u32 XV_HdmiRx1_DdcHdcpReadData </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
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<p>This function reads HDCP data from the DDC peripheral. </p>
<p>This is implemented as a function and not a macro, so the HDCP driver can bind the function call with a handler.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Rx core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns the HDCP data read from the DDC peripheral.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 XHdmiRx1_DdcHdcpReadData(XHdmi_Rx *InstancePtr) </dd></dl>

<p>References <a class="el" href="xv__hdmirx1__hw_8h.html#ada994691776136b75789d9e343b4ce08">XV_HDMIRX1_DDC_HDCP_DATA_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>.</p>

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          <td class="memname">void XV_HdmiRx1_DdcHdcpSetAddress </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Address</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function sets the HDCP address in the DDC peripheral. </p>
<p>This is implemented as a function and not a macro, so the HDCP driver can bind the function call with a handler.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Rx core instance. </td></tr>
    <tr><td class="paramname">Address</td><td>is the HDCP address.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XHdmiRx1_DdcHdcpSetAddress(XHdmi_Rx *InstancePtr, u8 Address) </dd></dl>

<p>References <a class="el" href="xv__hdmirx1__hw_8h.html#a8bbedc62df34078ef06647b7130e16f4">XV_HDMIRX1_DDC_HDCP_ADDRESS_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiRx1_DdcHdcpWriteData </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Data</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function writes HDCP data in the DDC peripheral. </p>
<p>This is implemented as a function and not a macro, so the HDCP driver can bind the function call with a handler.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Rx core instance. </td></tr>
    <tr><td class="paramname">Data</td><td>is the HDCP data to be written.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XHdmiRx1_DdcHdcpWriteData(XHdmi_Rx *InstancePtr, u8 Data) </dd></dl>

<p>References <a class="el" href="xv__hdmirx1__hw_8h.html#ada994691776136b75789d9e343b4ce08">XV_HDMIRX1_DDC_HDCP_DATA_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

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          <td class="memname">int XV_HdmiRx1_DdcIsHdcpReadMessageBufferEmpty </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function returns the status of the HDCP 2.2 read message buffer in the DDC slave. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Rx core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TRUE = HDCP 2.2 message buffer is empty.</li>
<li>FALSE = HDCP 2.2 message buffer contains data.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa2e6b62c7b7e30d408bd3743409310f9">XV_HDMIRX1_DDC_HDCP_STA_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ac65d331a8b1681442417b8a227c3e985">XV_HDMIRX1_DDC_STA_HDCP_RMSG_EP_MASK</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>.</p>

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          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function returns the status of the HDCP 2.2 write buffer in the DDC slave. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Rx core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TRUE = HDCP 2.2 message buffer is empty.</li>
<li>FALSE = HDCP 2.2 message buffer contains data.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa2e6b62c7b7e30d408bd3743409310f9">XV_HDMIRX1_DDC_HDCP_STA_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa097132dd0838bf692d390fc1e28cbc9">XV_HDMIRX1_DDC_STA_HDCP_WMSG_EP_MASK</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>.</p>

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          <td class="memname">int XV_HdmiRx1_DdcLoadEdid </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>EdidData</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>Length</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>This function loads the EDID data into the DDC slave. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance. </td></tr>
    <tr><td class="paramname">EdidData</td><td>is a pointer to the EDID data array. </td></tr>
    <tr><td class="paramname">Length</td><td>is the length, in bytes, of the EDID array.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if the EDID data was loaded successfully</li>
<li>XST_FAILURE if the EDID data load failed</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ad4057a137cbf824dbce306e040b82c49">XV_HDMIRX1_DDC_CTRL_EDID_EN_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a771754708a8fe2d29a65563db1a7a118">XV_HDMIRX1_DDC_CTRL_SET_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#abcfd19bf175b5a1df19606aecdb38d54">XV_HDMIRX1_DDC_EDID_DATA_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a41c54aba350be9952f7b1b154234c1d6">XV_HDMIRX1_DDC_EDID_WP_OFFSET</a>, <a class="el" href="xv__hdmirx1_8c.html#a071a1f439fe0d8c875eb7514984297a6">XV_HdmiRx1_DdcGetEdidWords()</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiRx1_DdcRegDump </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function prints out RX's SCDC registers and values on STDIO/UART. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ac5b57521457e46c5e347db1bd1d8ac28">XV_HDMIRX1_FRL_SCDC_ADDR_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a070a1c8c80d4f949700398f70e4c1184">XV_HDMIRX1_FRL_SCDC_DAT_SHIFT</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa5500d41f17295752a46f34a3f6ca2f3">XV_HDMIRX1_FRL_SCDC_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a96095a3a06333a80279343e58bd9a512">XV_HDMIRX1_FRL_SCDC_RD_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa89cb22259109c7e37ef35afa705782a">XV_HDMIRX1_FRL_SCDC_RDY_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiRx1_DebugInfo </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function prints debug information on STDIO/UART console. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a9db246d6864fa36907e4328865361617">XV_HDMIRX1_DBG_STA_LANE_LOCK_CHGALL_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a01fb2daa2e91e2578d672460d8e76a31">XV_HDMIRX1_DBG_STA_LANE_LOCK_CHGALL_SHIFT</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa7d3866d8c4fe0eb40668892c8907a6e">XV_HDMIRX1_DBG_STA_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ae71ca916fc1e751c0f5721bade5ab3b6">XV_HDMIRX1_DBG_STA_SCRM_LOCK_CHGALL_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a3d000d222218f9abca8a2dabd6626936">XV_HDMIRX1_DBG_STA_SCRM_LOCK_CHGALL_SHIFT</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aceb903127dc18e063143a5e9a63b1757">XV_HDMIRX1_DBG_STA_SKEW_LOCK_CHG_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#af2f364dc06424596ccc3ad6ab2b5e547">XV_HDMIRX1_DBG_STA_WA_LOCK_CHGALL_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ac99474f377d76e370d9dde2c72fac684">XV_HDMIRX1_DBG_STA_WA_LOCK_CHGALL_SHIFT</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a9ee121571671ab263e18f314daa4e822">XV_HDMIRX1_DBG_STA_WA_TAP_CHGALL_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a566bd6a5e931c701ab04941f556b7817">XV_HDMIRX1_FRL_ERR_CNT1_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a1a5393b88617a33dff7527a0c7a3f84c">XV_HDMIRX1_FRL_RATIO_ACT_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a9607aefecf7958adf00b11faaca7ceb0">XV_HDMIRX1_FRL_RATIO_TOT_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a95df122fd8f593ac94504abaff87fecb">XV_HDMIRX1_FRL_RSFC_CNT_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a819ca83e4c0169868874dc344b97e0f9">XV_HDMIRX1_FRL_STA_FRL_LANES_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a2c5d7ff6904298bf55ccaa3ad1e52209">XV_HDMIRX1_FRL_STA_FRL_MODE_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a9ce5dbbe22e0e4254cec1e5c1e791b9e">XV_HDMIRX1_FRL_STA_FRL_RATE_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a9ae67cbce6039396d76e9fae77871960">XV_HDMIRX1_FRL_STA_FRL_RATE_SHIFT</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a14fa43a8eb929f9834823a037557c755">XV_HDMIRX1_FRL_STA_LANE_LOCK_ALLL_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#af3ce4c26d43187cdd23935f92d00772b">XV_HDMIRX1_FRL_STA_LANE_LOCK_ALLL_SHIFT</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a96860e2915010d82971cc380b30d30fd">XV_HDMIRX1_FRL_STA_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a47ebab7f2a605e29b68f2121c1bde7d7">XV_HDMIRX1_FRL_STA_SCRM_LOCK_ALLL_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a4fb39fe8225243a7a63b683cde0e772c">XV_HDMIRX1_FRL_STA_SCRM_LOCK_ALLL_SHIFT</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa1fb32957e468cc337ac7ce5828a0b50">XV_HDMIRX1_FRL_STA_SKEW_LOCK_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#afdfa16dd3c11af7a70bf3743f3c5dbd3">XV_HDMIRX1_FRL_STA_STR_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#abe2e332e4def7d78b9692fcfe5dceb3a">XV_HDMIRX1_FRL_STA_VID_LOCK_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa4a2f8e85cba03c8b0eb1a230b2f89c4">XV_HDMIRX1_FRL_STA_WA_LOCK_ALLL_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a55c84609819cd4f182160813cff62ffe">XV_HDMIRX1_FRL_STA_WA_LOCK_ALLL_SHIFT</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a49b8c41fcbbd455844d641a215d6eae8">XV_HDMIRX1_FRL_VID_LOCK_CNT_OFFSET</a>, <a class="el" href="xv__hdmirx1_8h.html#abcaa2a7e3e0a31a5d19b99179e70c636">XV_HdmiRx1_GetFrlActivePixRatio()</a>, <a class="el" href="xv__hdmirx1_8h.html#afd29a2caefd6060c3546e3debe17f03b">XV_HdmiRx1_GetFrlTotalPixRatio()</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ae1aaa652d8211c7cc612dd506aeb480d">XV_HDMIRX1_LNKSTA_STA_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#af4dcda505ba0f225b5b8c9cb9a3c1389">XV_HDMIRX1_PIO_IN_ALIGNER_LOCK_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a9e9029db2aff750b7c208c8eca7faff9">XV_HDMIRX1_PIO_IN_MODE_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a49992379740fbcb1480c2ea6aa8709c2">XV_HDMIRX1_PIO_IN_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a7d01e744c692ff9a143309dd407196a9">XV_HDMIRX1_PIO_IN_SCRAMBLER_LOCKALLL_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#afbf01122ade2aaaf05f758fb22095341">XV_HDMIRX1_PIO_IN_SCRAMBLER_LOCKALLL_SHIFT</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#af3377eb2df940c5697d67f58e08cd20f">XV_HDMIRX1_PKT_ECC_ERR_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a601ed84adad6a742a16572b1394049f7">XV_HDMIRX1_SR_SSB_ERR1_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ace563a6b75eaca93062466c5fb31d3c8">XV_HDMIRX1_SR_SSB_ERR2_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a505ad0065028146badda00bb46ef8100">XV_HDMIRX1_SR_SSB_ERR2_SHIFT</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#adfbfa70ecfc15e9951eed4a41333b8e1">XV_HDMIRX1_SR_SSB_ERR_CNT0_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ae366ca39c9b39631eedf90c9df008502">XV_HDMIRX1_SR_SSB_ERR_CNT1_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a38593421477cf0920a8c26ca2cc02844">XV_HDMIRX1_SR_SSB_ERR_CNT2_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a280f061931e044ccdc8aa667114f17e5">XV_HDMIRX1_SR_SSB_ERR_CNT3_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a161cbe93ae2eadf4572c49ddac875dd9">XV_HDMIRX1_TRIB_ANLZ_LN_ACT_ACT_SZ_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a117109a90e42e3017e55fbfc7ebd9966">XV_HDMIRX1_TRIB_ANLZ_LN_ACT_LN_SZ_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aae138c58ab74045375d385644647ebf5">XV_HDMIRX1_TRIB_ANLZ_LN_ACT_LN_SZ_SHIFT</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#af450e13abf1a60b31de267c985fffbaa">XV_HDMIRX1_TRIB_ANLZ_LN_ACT_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a5bbac44be7ff425765198c35f15ee990">XV_HDMIRX1_TRIB_ANLZ_TIM_CHGD_CNT_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a25030374b218ae27a165342023eb26f6">XV_HDMIRX1_TRIB_ANLZ_TIM_HS_POL_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ad74412e1cce4c05dc20962e823caaa2e">XV_HDMIRX1_TRIB_ANLZ_TIM_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aefd7163342d38fe7440ac8cb178bb734">XV_HDMIRX1_TRIB_ANLZ_TIM_VS_POL_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a1cef14123da432543b502426ea4ba921">XV_HDMIRX1_TRIB_HBP_HS_HBP_SZ_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ac1ff018afd4c825fae5d24a0d99397c8">XV_HDMIRX1_TRIB_HBP_HS_HBP_SZ_SHIFT</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a290b6094a24ee78187d80ce9e3bac2bf">XV_HDMIRX1_TRIB_HBP_HS_HS_SZ_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a8ecc8705595c3f5ef2efdefea908ef19">XV_HDMIRX1_TRIB_HBP_HS_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a7c9d08be5e87e6fd62df99abfd8d3a07">XV_HDMIRX1_VCKE_SYS_CNT_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a98c2ec7a077e707ff67302d576ba468f">XV_HDMIRX1_VER_ID_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a8b63858c4f1f73528819cac7258bc730">XV_HDMIRX1_VER_VERSION_OFFSET</a>.</p>

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          <td class="memname">u32 XV_HdmiRx1_Divide </td>
          <td>(</td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Dividend</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Divisor</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function calculates the divider for the frame calculation. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Dividend</td><td>is the dividend value to use in the calculation. </td></tr>
    <tr><td class="paramname">Divisor</td><td>is the divisor value to use in the calculation.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The result of the calculation.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

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          <td class="memname">void XV_HdmiRx1_DynHDR_GetInfo </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1___dyn_h_d_r___info.html">XV_HdmiRx1_DynHDR_Info</a> *&#160;</td>
          <td class="paramname"><em>RxDynHdrInfoPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function gets the Dynamic HDR packet type, length, whether graphics overlay and errors if any. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmiRx1 core instance. </td></tr>
    <tr><td class="paramname">RxDynHdrInfoPtr</td><td>is a pointer to XHdmiRx1 Dynamic HDR info instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="struct_x_v___hdmi_rx1___config.html#a429bd4e2abdedeb2f459e2bc9cd7723c">XV_HdmiRx1_Config::DynamicHDR</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a3ad16e42fdc47d009ff567cbf65d7ca0">XV_HDMIRX1_AUX_DYN_HDR_INFO_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#add06acac6296880fa714d3265160890d">XV_HDMIRX1_AUX_DYN_HDR_STS_ERR_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a52d316fb63d45bfdcd8def3b5503ef03">XV_HDMIRX1_AUX_DYN_HDR_STS_GOF_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#abd7ef1376fabe26cb32ece3c4efa7450">XV_HDMIRX1_AUX_DYN_HDR_STS_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>.</p>

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          <td class="memname">void XV_HdmiRx1_DynHDR_SetAddr </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u64&#160;</td>
          <td class="paramname"><em>Addr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function sets the Dynamic HDR buffer address. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmiRx1 core instance. </td></tr>
    <tr><td class="paramname">Addr</td><td>is an address in 64bit format.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="struct_x_v___hdmi_rx1___config.html#a429bd4e2abdedeb2f459e2bc9cd7723c">XV_HdmiRx1_Config::DynamicHDR</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ab0a5740fe6d10b7c283a683e745518cf">XV_HDMIRX1_AUX_DYN_HDR_MEMADDR_LSB_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a94fec423e8bda97ee8cf9a7939e55aa5">XV_HDMIRX1_AUX_DYN_HDR_MEMADDR_MSB_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

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          <td class="memname">int XV_HdmiRx1_ExecFrlState </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function executes the different of states of FRL. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1.html#adf8543d358aeaf359d915412003845e3">XV_HdmiRx1::Stream</a>, and <a class="el" href="struct_x_v___hdmi_rx1___frl.html#a0eb1fb5490f5c6416d49455599444083">XV_HdmiRx1_Frl::TrainingState</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#a07be19e39e2a3e90ea9ac937f6adfc58">XV_HdmiRx1_FrlLinkRetrain()</a>, and <a class="el" href="xv__hdmirx1__frl_8c.html#a8b8df1df4274fd34afc6ad600c4d1605">XV_HdmiRx1_FrlModeEnable()</a>.</p>

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          <td class="memname">void XV_HdmiRx1_EXT_SYSRST </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Reset</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function asserts or releases the HDMI RX External SYSRST. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance. </td></tr>
    <tr><td class="paramname">Reset</td><td>specifies TRUE/FALSE value to either assert or release HDMI RX External SYSRST.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The reset output of the PIO is inverted. When the system is in reset, the PIO output is cleared and this will reset the HDMI RX. Therefore, clearing the PIO reset output will assert the HDMI External system reset. C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#af441b03cc79286c209dbffed19fc6052" title="This function asserts or releases the HDMI RX External SYSRST. ">XV_HdmiRx1_EXT_SYSRST(XV_HdmiRx1 *InstancePtr, u8 Reset)</a> </dd></dl>

<p>References <a class="el" href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#af4e73625cd9540a0f4885dd41afd95eb">XV_HDMIRX1_PIO_OUT_EXT_SYSRST_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiRx1_EXT_VRST </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Reset</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function asserts or releases the HDMI RX External VRST. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance. </td></tr>
    <tr><td class="paramname">Reset</td><td>specifies TRUE/FALSE value to either assert or release HDMI RX External VRST.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The reset output of the PIO is inverted. When the system is in reset, the PIO output is cleared and this will reset the HDMI RX. Therefore, clearing the PIO reset output will assert the HDMI external video reset. C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#aba149130be3e337c3789bd0fcf3c8481" title="This function asserts or releases the HDMI RX External VRST. ">XV_HdmiRx1_EXT_VRST(XV_HdmiRx1 *InstancePtr, u8 Reset)</a> </dd></dl>

<p>References <a class="el" href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a67959c83fa1faaaccb685a9070cec447">XV_HDMIRX1_PIO_OUT_EXT_VRST_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

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          <td class="memname">u32 XV_HdmiRx1_FrlDdcReadField </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XV_HdmiRx1_FrlScdcFieldType&#160;</td>
          <td class="paramname"><em>Field</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function reads the specified FRL SCDC Field. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
    <tr><td class="paramname">Field</td><td>specifies the fields from SCDC channels to be written</td></tr>
    <tr><td class="paramname">Value</td><td>specifies the values to be written</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS</li>
<li>XST_FAILURE</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="struct_x_v___hdmi_rx1___frl_scdc_field.html#a7ca76af091ecb7c7a9e46cf8c292ed94">XV_HdmiRx1_FrlScdcField::Offset</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ac5b57521457e46c5e347db1bd1d8ac28">XV_HDMIRX1_FRL_SCDC_ADDR_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a070a1c8c80d4f949700398f70e4c1184">XV_HDMIRX1_FRL_SCDC_DAT_SHIFT</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa5500d41f17295752a46f34a3f6ca2f3">XV_HDMIRX1_FRL_SCDC_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a96095a3a06333a80279343e58bd9a512">XV_HDMIRX1_FRL_SCDC_RD_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa89cb22259109c7e37ef35afa705782a">XV_HDMIRX1_FRL_SCDC_RDY_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#ab17e4f96ebbe6785b411233165de859a">XV_HdmiRx1_FrlDdcWriteField()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#a6010db11abd7d7a7b935d20b693c5b7a">XV_HdmiRx1_GetFrlLtpDetection()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#a580b1f726297a49e552e2e90aa7a80f4">XV_HdmiRx1_RetrieveFrlRateLanes()</a>, and <a class="el" href="xv__hdmirx1_8h.html#a8fde9d6293c66dde0cb3d18dfbf2375a">XV_HdmiRx1_UpdateEdFlags()</a>.</p>

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          <td class="memname">int XV_HdmiRx1_FrlDdcWriteField </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XV_HdmiRx1_FrlScdcFieldType&#160;</td>
          <td class="paramname"><em>Field</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Value</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function writes the specified FRL SCDC Field. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
    <tr><td class="paramname">Field</td><td>specifies the fields from SCDC channels to be written</td></tr>
    <tr><td class="paramname">Value</td><td>specifies the values to be written</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS</li>
<li>XST_FAILURE</li>
<li>XST_DEVICE_BUSY</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="struct_x_v___hdmi_rx1___frl_scdc_field.html#aecbfb387e752c5723ec6ac15d73dd268">XV_HdmiRx1_FrlScdcField::Mask</a>, <a class="el" href="struct_x_v___hdmi_rx1___frl_scdc_field.html#acb6b6b9a6a07477a53365e9f879ac168">XV_HdmiRx1_FrlScdcField::Shift</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ac5b57521457e46c5e347db1bd1d8ac28">XV_HDMIRX1_FRL_SCDC_ADDR_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#afc293c2e58cd8a42b857d83e4cb388b5">XV_HDMIRX1_FRL_SCDC_DAT_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a070a1c8c80d4f949700398f70e4c1184">XV_HDMIRX1_FRL_SCDC_DAT_SHIFT</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa5500d41f17295752a46f34a3f6ca2f3">XV_HDMIRX1_FRL_SCDC_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa89cb22259109c7e37ef35afa705782a">XV_HDMIRX1_FRL_SCDC_RDY_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#affb659995dc3b980da1ecf2bea25f794">XV_HDMIRX1_FRL_SCDC_WR_MASK</a>, <a class="el" href="xv__hdmirx1_8h.html#a38c0efa82d512c42b07775e36f919bb2">XV_HdmiRx1_FrlDdcReadField()</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#a04b941fdfc281d7d81665d47ac32f1d2">XV_HdmiRx1_FrlReset()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#adf3222be232d5b0eaabeb5fbba4258fa">XV_HdmiRx1_SetFrlLtpDetection()</a>, and <a class="el" href="xv__hdmirx1_8h.html#a8fde9d6293c66dde0cb3d18dfbf2375a">XV_HdmiRx1_UpdateEdFlags()</a>.</p>

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          <td class="memname">void XV_HdmiRx1_FrlLinkRetrain </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>LtpThreshold</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XV_HdmiRx1_FrlLtp&#160;</td>
          <td class="paramname"><em>DefaultLtp</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function initiates FRL rate dropping procedure. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
    <tr><td class="paramname">LtpThreshold</td><td>specifies the number of times the LTP matching module must match against the incoming link training pattern before a match is indicated</td></tr>
    <tr><td class="paramname">DefaultLtp</td><td>specify the link training pattern which will be used for link training purposes<ul>
<li>XV_HDMIRX1_LTP_LFSR0</li>
<li>XV_HDMIRX1_LTP_LFSR1</li>
<li>XV_HDMIRX1_LTP_LFSR2</li>
<li>XV_HDMIRX1_LTP_LFSR3</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Status on if FrlTraining can be started or not.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___frl.html#a0f554039b7fe90c629cb245a727540b7">XV_HdmiRx1_Frl::DefaultLtp</a>, <a class="el" href="struct_x_v___hdmi_rx1___frl.html#a21a4013614c2eae5fd14968ad790c669">XV_HdmiRx1_Frl::Ltp</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#adf8543d358aeaf359d915412003845e3">XV_HdmiRx1::Stream</a>, <a class="el" href="struct_x_v___hdmi_rx1___frl.html#a0eb1fb5490f5c6416d49455599444083">XV_HdmiRx1_Frl::TrainingState</a>, <a class="el" href="xv__hdmirx1_8h.html#adaa4205184958f79b8aa3d2e39b97661">XV_HdmiRx1_ExecFrlState()</a>, and <a class="el" href="xv__hdmirx1_8h.html#a095b12f733544b877279ea062c592a7d">XV_HdmiRx1_SetFrlLtpThreshold()</a>.</p>

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          <td class="memname">void XV_HdmiRx1_FrlLtpDetectionDisable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function disables the LTP detection module. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa929db9fe8649faf5c094fb703fd82f9">XV_HDMIRX1_FRL_CTRL_FLT_CLR_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a32a9590fef5f8526e7c68b2ce8e88f89">XV_HDMIRX1_FRL_CTRL_SET_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiRx1_FrlLtpDetectionEnable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
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<p>This function enables the LTP detection module. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a445d11205376c2220586ddd6c01fb423">XV_HDMIRX1_FRL_CTRL_CLR_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa929db9fe8649faf5c094fb703fd82f9">XV_HDMIRX1_FRL_CTRL_FLT_CLR_MASK</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiRx1_FrlModeEnable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>LtpThreshold</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XV_HdmiRx1_FrlLtp&#160;</td>
          <td class="paramname"><em>DefaultLtp</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>FfeSuppFlag</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function enables the FRL mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
    <tr><td class="paramname">LtpThreshold</td><td>specifies the number of times the LTP matching module must match against the incoming link training pattern before a match is indicated</td></tr>
    <tr><td class="paramname">DefaultLtp</td><td>specify the link training pattern which will be used for link training purposes<ul>
<li>XV_HDMIRX1_LTP_LFSR0</li>
<li>XV_HDMIRX1_LTP_LFSR1</li>
<li>XV_HDMIRX1_LTP_LFSR2</li>
<li>XV_HDMIRX1_LTP_LFSR3</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Status on if FrlTraining can be started or not.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___frl.html#a0f554039b7fe90c629cb245a727540b7">XV_HdmiRx1_Frl::DefaultLtp</a>, <a class="el" href="struct_x_v___hdmi_rx1___frl.html#a52827fe0fcf8a35db1def1910fada68d">XV_HdmiRx1_Frl::FfeSuppFlag</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#adf8543d358aeaf359d915412003845e3">XV_HdmiRx1::Stream</a>, <a class="el" href="struct_x_v___hdmi_rx1___frl.html#a0eb1fb5490f5c6416d49455599444083">XV_HdmiRx1_Frl::TrainingState</a>, <a class="el" href="xv__hdmirx1_8h.html#adaa4205184958f79b8aa3d2e39b97661">XV_HdmiRx1_ExecFrlState()</a>, and <a class="el" href="xv__hdmirx1_8h.html#a095b12f733544b877279ea062c592a7d">XV_HdmiRx1_SetFrlLtpThreshold()</a>.</p>

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          <td class="memname">void XV_HdmiRx1_FrlReset </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Reset</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>This function resets the FRL peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
    <tr><td class="paramname">Reset</td><td>specifies if the FRL peripheral is under reset or not.<ul>
<li>0 = Reset released</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<ul>
<li>1 = Reset asserted</li>
</ul>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a445d11205376c2220586ddd6c01fb423">XV_HDMIRX1_FRL_CTRL_CLR_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a21d52c1e98512bf55931aba594323451">XV_HDMIRX1_FRL_CTRL_RSTN_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a32a9590fef5f8526e7c68b2ce8e88f89">XV_HDMIRX1_FRL_CTRL_SET_OFFSET</a>, <a class="el" href="xv__hdmirx1_8h.html#ab17e4f96ebbe6785b411233165de859a">XV_HdmiRx1_FrlDdcWriteField()</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx1_8h.html#ac7552beea455de7ac51452cb284241f3">XV_HdmiRx1_SetHpd()</a>.</p>

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          <td class="memname">u32 XV_HdmiRx1_GetAcrCts </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function provides audio clock regenerating CTS (Cycle-Time Stamp) value at the HDMI sink device. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Audio clock CTS value.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a29e933929edb889a5cf22e2b358bcbd6">XV_HDMIRX1_AUD_CTS_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>.</p>

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          <td class="memname">u32 XV_HdmiRx1_GetAcrN </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function provides audio clock regenerating factor N value. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>ACR N value.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa108342fb6a7cb47e297368082ba4943">XV_HDMIRX1_AUD_N_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>.</p>

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          <td class="memname">XVidC_ColorFormat XV_HdmiRx1_GetAviColorSpace </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function returns the AVI colorspace (captured by the AUX peripheral) </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The AVI colorspace value.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ae4df89df74ea61966284a00390fc2754">XV_HDMIRX1_AUX_STA_AVI_CS_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ade847b0f35ba1afad9843e799adb7bbe">XV_HDMIRX1_AUX_STA_AVI_CS_SHIFT</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a1ff1aa131b92f22cdadf41f72b41de10">XV_HDMIRX1_AUX_STA_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a77f3a5723008c8604137960daa6174bd">XV_HdmiRx1_GetVideoProperties()</a>.</p>

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          <td class="memname">u8 XV_HdmiRx1_GetAviVic </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function returns the AVI VIC (captured by the AUX peripheral) </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The AVI VIC code.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a7ab9bb403ffe88b36b5ad9f8dc1b28aa">XV_HDMIRX1_AUX_STA_AVI_VIC_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#abffc2c8a5b1e99d2698108754af68ee2">XV_HDMIRX1_AUX_STA_AVI_VIC_SHIFT</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a1ff1aa131b92f22cdadf41f72b41de10">XV_HDMIRX1_AUX_STA_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a77f3a5723008c8604137960daa6174bd">XV_HdmiRx1_GetVideoProperties()</a>.</p>

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          <td class="memname">u32 XV_HdmiRx1_GetFrlActivePixRatio </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function provides FRL Ratio (Active Pixel) </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>FRL Clock Ratio (Active Pixel)</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a1a5393b88617a33dff7527a0c7a3f84c">XV_HDMIRX1_FRL_RATIO_ACT_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

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          <td class="memname">u32 XV_HdmiRx1_GetFrlLtpDetection </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Lane</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function returns the link training pattern to be detected for the selected lane. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
    <tr><td class="paramname">Lane</td><td>specifies the lane of which the Link Training Pattern will be returned.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Link Training Pattern<ul>
<li>5 = LTP5 / LFSR 0</li>
<li>6 = LTP6 / LFSR 1</li>
<li>7 = LTP7 / LFSR 2</li>
<li>8 = LTP8 / LFSR 3</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmirx1_8h.html#a38c0efa82d512c42b07775e36f919bb2">XV_HdmiRx1_FrlDdcReadField()</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#ad8f801766bca274f8235adde45ddc085">XV_HdmiRx1_ConfigFrlLtpDetection()</a>.</p>

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          <td class="memname">u32 XV_HdmiRx1_GetFrlTotalPixRatio </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function provides FRL Ratio (Total Pixel) </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>FRL Clock Ratio (Total Pixel)</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a9607aefecf7958adf00b11faaca7ceb0">XV_HDMIRX1_FRL_RATIO_TOT_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

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          <td class="memname">XVidC_ColorDepth XV_HdmiRx1_GetGcpColorDepth </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function returns the GCP color depth (captured by the AUX peripheral) </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The GCP color depth.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a42156911fe2a4d3c5ac885ab25f63008">XV_HDMIRX1_AUX_STA_GCP_CD_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa32fc692224b983ed8c19d6667bcb3d8">XV_HDMIRX1_AUX_STA_GCP_CD_SHIFT</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a1ff1aa131b92f22cdadf41f72b41de10">XV_HDMIRX1_AUX_STA_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a77f3a5723008c8604137960daa6174bd">XV_HdmiRx1_GetVideoProperties()</a>.</p>

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          <td class="memname">u32 XV_HdmiRx1_GetLinkStatus </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Type</em>&#160;</td>
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        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function provides status of the HDMI RX core Link Status peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance. </td></tr>
    <tr><td class="paramname">Type</td><td>specifies one of the type for which status to be provided:<ul>
<li>0 = Link error counter for channel 0.</li>
<li>1 = Link error counter for channel 1.</li>
<li>2 = Link error counter for channel 2.</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Link status of the HDMI RX core link.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a87138c8927cdc27db845edb3556a82c8">XV_HDMIRX1_LNKSTA_LNK_ERR0_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>.</p>

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          <td class="memname">u32 XV_HdmiRx1_GetPatternsMatchStatus </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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      </table>
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<p>This function returns the status of the patterns matched lanes. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a7ddf3b09dbf2981e2dd320fdb3fd3115">XV_HDMIRX1_FRL_STA_FLT_PM_ALLL_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a290ac811254db762d363a1f1a69e23d3">XV_HDMIRX1_FRL_STA_FLT_PM_ALLL_SHIFT</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a96860e2915010d82971cc380b30d30fd">XV_HDMIRX1_FRL_STA_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#adebf854f66fb92c37366faab549dd4a8">XV_HdmiRx1_PhyResetPoll()</a>.</p>

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          <td class="memname">int XV_HdmiRx1_GetTmdsClockRatio </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function gets the SCDC TMDS clock ratio bit. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TRUE = TMDS clock ratio bit is set.</li>
<li>FALSE = TMDS clock ratio bit is cleared.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a49992379740fbcb1480c2ea6aa8709c2">XV_HDMIRX1_PIO_IN_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a51d2852cd78f9a896e224454b97f092b">XV_HDMIRX1_PIO_IN_SCDC_TMDS_CLOCK_RATIO_MASK</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>.</p>

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          <td class="memname">int XV_HdmiRx1_GetVideoProperties </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
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<p>This function reads the video properties from the aux peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#adf8543d358aeaf359d915412003845e3">XV_HdmiRx1::Stream</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a22196adeeb4add191c26302017bfb8da">XV_HDMIRX1_AUX_STA_AVI_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a1ff1aa131b92f22cdadf41f72b41de10">XV_HDMIRX1_AUX_STA_OFFSET</a>, <a class="el" href="xv__hdmirx1_8c.html#ad4f280e6064c750dcc09cdd3bdcaa408">XV_HdmiRx1_GetAviColorSpace()</a>, <a class="el" href="xv__hdmirx1_8c.html#ab77058d12d39a6cae1920402ad231de8">XV_HdmiRx1_GetAviVic()</a>, <a class="el" href="xv__hdmirx1_8c.html#a4c6e4ca31c0b284eaa58924dd42d1d13">XV_HdmiRx1_GetGcpColorDepth()</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>.</p>

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          <td class="memname">int XV_HdmiRx1_GetVideoTiming </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function reads the video timing from the VTD peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#adf8543d358aeaf359d915412003845e3">XV_HdmiRx1::Stream</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a815bc83c2185567b85fc6e6261af9d8c">XV_HdmiRx1::VrrIF</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ae6e5fdc512cb7dc4f87aa5ddf8d87044">XV_HDMIRX1_VTD_ACT_LIN_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aaf231b8bf27d043648c5d4c18570e109">XV_HDMIRX1_VTD_ACT_PIX_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a29d81fca1318aa8e6dcb266ebf3eaf49">XV_HDMIRX1_VTD_HBP_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aefb8dcc326ae1f421f1755d7eae42f2c">XV_HDMIRX1_VTD_HFP_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ad49d4b9701fc528d4b35be9e0e0784b6">XV_HDMIRX1_VTD_HSW_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a1d7f91b7dd9418376b0f3b3ad33dffa9">XV_HDMIRX1_VTD_STA_FMT_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ac65a4d1a61da0cc29958b992c6096bc7">XV_HDMIRX1_VTD_STA_HS_POL_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a7520909f353bdbc6da5cf59e436c0346">XV_HDMIRX1_VTD_STA_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a8451cdcae193a13f05a07d2b1d7c46f5">XV_HDMIRX1_VTD_STA_VS_POL_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a1130ed99163f49891fe76e84a2fd1ee0">XV_HDMIRX1_VTD_TOT_LIN_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a31173bdc12d5d7c393e0ec4169a0e9bc">XV_HDMIRX1_VTD_TOT_PIX_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a655cb29d88325aab2476894e18a858fe">XV_HDMIRX1_VTD_VBP_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a8b283a7d946febcf50815dc8ad31bf8d">XV_HDMIRX1_VTD_VFP_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a881c6ffd3db18a7af39fe337d00eb179">XV_HDMIRX1_VTD_VSW_OFFSET</a>.</p>

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          <td class="memname">XV_HdmiC_VrrInfoframeType XV_HdmiRx1_GetVrrIfType </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function returns VRR infoframe type. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmiRx1 core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>XV_HdmiRx1_VrrInfoframeType</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1.html#a815bc83c2185567b85fc6e6261af9d8c">XV_HdmiRx1::VrrIF</a>.</p>

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          <td class="memname">void XV_HdmiRx1_Info </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
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<p>This function prints stream and timing information on STDIO/UART console. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1.html#adf8543d358aeaf359d915412003845e3">XV_HdmiRx1::Stream</a>.</p>

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          <td class="memname">void XV_HdmiRx1_INT_LRST </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Reset</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>This function asserts or releases the HDMI RX Internal LRST. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance. </td></tr>
    <tr><td class="paramname">Reset</td><td>specifies TRUE/FALSE value to either assert or release HDMI RX Internal LRST.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The reset output of the PIO is inverted. When the system is in reset, the PIO output is cleared and this will reset the HDMI RX. Therefore, clearing the PIO reset output will assert the HDMI Internal link reset. C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a54c8f8e466187861aeeb7f1de53839c4" title="This function asserts or releases the HDMI RX Internal VRST. ">XV_HdmiRx1_INT_VRST(XV_HdmiRx1 *InstancePtr, u8 Reset)</a> </dd></dl>

<p>References <a class="el" href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a40d80538fcb5bc6ae4dd18590766b12c">XV_HDMIRX1_PIO_OUT_INT_LRST_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiRx1_INT_VRST </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Reset</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>This function asserts or releases the HDMI RX Internal VRST. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance. </td></tr>
    <tr><td class="paramname">Reset</td><td>specifies TRUE/FALSE value to either assert or release HDMI RX Internal VRST.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The reset output of the PIO is inverted. When the system is in reset, the PIO output is cleared and this will reset the HDMI RX. Therefore, clearing the PIO reset output will assert the HDMI Internal video reset. C-style signature: void <a class="el" href="xv__hdmirx1_8h.html#a54c8f8e466187861aeeb7f1de53839c4" title="This function asserts or releases the HDMI RX Internal VRST. ">XV_HdmiRx1_INT_VRST(XV_HdmiRx1 *InstancePtr, u8 Reset)</a> </dd></dl>

<p>References <a class="el" href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a12d07ceb2b0cf661463eace18d19b370">XV_HDMIRX1_PIO_OUT_INT_VRST_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiRx1_IntrHandler </td>
          <td>(</td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function is the interrupt handler for the HDMI RX driver. </p>
<p>This handler reads the pending interrupt from PIO, DDC, TIMDET, AUX, AUD and LNKSTA peripherals, determines the source of the interrupts, clears the interrupts and calls callbacks accordingly.</p>
<p>The application is responsible for connecting this function to the interrupt system. Application beyond this driver is also responsible for providing callbacks to handle interrupts and installing the callbacks using <a class="el" href="xv__hdmirx1_8h.html#a7039dd1c40555eb136d7fcddda44d7b0" title="This function installs an asynchronous callback function for the given HandlerType: ...">XV_HdmiRx1_SetCallback()</a> during initialization phase. An example delivered with this driver demonstrates how this could be done.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> instance that just interrupted.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a702c45e45b496ad8b6aa51238a8b5bb2">XV_HdmiRx1::IsReady</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a9b671fa1d778ce26fb96731f95660999">XV_HDMIRX1_AUD_STA_IRQ_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a6b471c291404420baf14808dc39da8e4">XV_HDMIRX1_AUD_STA_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a63d7aee7a102a56cf637518d13307a12">XV_HDMIRX1_AUX_STA_IRQ_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a1ff1aa131b92f22cdadf41f72b41de10">XV_HDMIRX1_AUX_STA_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a1e194d82be050c88db0b276f30058fc1">XV_HDMIRX1_DDC_STA_IRQ_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a4b377386dc2f94f5fb4e17fb151245ab">XV_HDMIRX1_DDC_STA_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a19aa4846875e36f3df281003be17365b">XV_HDMIRX1_FRL_STA_IRQ_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a96860e2915010d82971cc380b30d30fd">XV_HDMIRX1_FRL_STA_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#affc58e86fdd9965c66c1787293747fe7">XV_HDMIRX1_LNKSTA_STA_IRQ_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ae1aaa652d8211c7cc612dd506aeb480d">XV_HDMIRX1_LNKSTA_STA_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a0d4a80745016667fabf3927fb58bc835">XV_HDMIRX1_PIO_STA_IRQ_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a010800518b582144dfb9dcc66525faf6">XV_HDMIRX1_PIO_STA_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#af91d2f9f96e679cac7647029f58ec4f7">XV_HDMIRX1_TMR_STA_IRQ_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a4afca904429b1f2e882bea212effe1cf">XV_HDMIRX1_TMR_STA_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a979add2356c64b6b17d2e173b148a223">XV_HDMIRX1_VTD_STA_IRQ_MASK</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a7520909f353bdbc6da5cf59e436c0346">XV_HDMIRX1_VTD_STA_OFFSET</a>.</p>

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          <td class="memname">int XV_HdmiRx1_IsLinkStatusErrMax </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function provides status of one of the link error counters reached the maximum value. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TRUE = Maximum error counter reached.</li>
<li>FALSE = Maximum error counter not reached.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ac8d20de61b9c7d747c78d766aeaec51c">XV_HDMIRX1_LNKSTA_STA_ERR_MAX_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ae1aaa652d8211c7cc612dd506aeb480d">XV_HDMIRX1_LNKSTA_STA_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>.</p>

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          <td class="memname">int XV_HdmiRx1_IsStreamConnected </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function provides the stream connected status. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TRUE = Stream is connected.</li>
<li>FALSE = Stream is connected.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1.html#adf8543d358aeaf359d915412003845e3">XV_HdmiRx1::Stream</a>.</p>

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          <td class="memname">int XV_HdmiRx1_IsStreamScrambled </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function provides the stream scrambler status. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TRUE = Stream is scrambled.</li>
<li>FALSE = Stream is not scrambled.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1.html#adf8543d358aeaf359d915412003845e3">XV_HdmiRx1::Stream</a>.</p>

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          <td class="memname">int XV_HdmiRx1_IsStreamUp </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function provides status of the stream. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TRUE = Stream is up.</li>
<li>FALSE = Stream is down.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1.html#adf8543d358aeaf359d915412003845e3">XV_HdmiRx1::Stream</a>, and <a class="el" href="xv__hdmirx1_8h.html#aaff80d21f94c4b494ab6beb909f74ebaa78cc6e34272e81a858d62f92557a3950">XV_HDMIRX1_STATE_STREAM_UP</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_v___hdmi_rx1___config.html">XV_HdmiRx1_Config</a>* XV_HdmiRx1_LookupConfig </td>
          <td>(</td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
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<p>This function returns a reference to an <a class="el" href="struct_x_v___hdmi_rx1___config.html" title="This typedef contains configuration information for the HDMI RX core. ">XV_HdmiRx1_Config</a> structure based on the core id, <em>DeviceId</em>. </p>
<p>The return value will refer to an entry in the device configuration table defined in the xv_hdmirx1_g.c file.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>is the unique core ID of the HDMI RX core for the lookup operation.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>XV_HdmiRx1_LookupConfig returns a reference to a config record in the configuration table (in xv_hdmirx1_g.c) corresponding to <em>DeviceId</em>, or NULL if no match is found.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

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          <td class="memname">XVidC_VideoMode XV_HdmiRx1_LookupVmId </td>
          <td>(</td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Vic</em></td><td>)</td>
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<p>This function searches for the video mode based on the vic. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Vic</td><td></td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Vic defined in the VIC table.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

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          <td class="memname">void XV_HdmiRx1_PhyResetPoll </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function polls the pattern matching status and decide if the Phy needs to be reset or not. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___frl.html#a5e7fe7b2df2ad8498ac0605f9c8de79b">XV_HdmiRx1_Frl::Lanes</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ab7df9f45764e36ab61362f08614461d5">XV_HdmiRx1::PhyResetCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ae134dc0565019f363f41fcb807a2e4c9">XV_HdmiRx1::PhyResetRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#adf8543d358aeaf359d915412003845e3">XV_HdmiRx1::Stream</a>, <a class="el" href="xv__hdmirx1_8h.html#af9ac94749a5d49d68879dda13618a3fd">XV_HdmiRx1_GetPatternsMatchStatus()</a>, and <a class="el" href="xv__hdmirx1_8c.html#af10ef171597554725eb963e6ee83278b">XV_HdmiRx1_TmrStartMs()</a>.</p>

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          <td class="memname">void XV_HdmiRx1_RegisterDebug </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function prints out HDMI RX register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a49b8c41fcbbd455844d641a215d6eae8">XV_HDMIRX1_FRL_VID_LOCK_CNT_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>.</p>

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          <td class="memname">void XV_HdmiRx1_ResetFrlLtpDetection </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function reset the link training pattern for the specified lane. </p>
<p>This is needed whenever the link training pattern is changed or the RxFFE is changed.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
    <tr><td class="paramname">Lane</td><td>specifies the lane of which the Link Training Pattern will be detected for.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a445d11205376c2220586ddd6c01fb423">XV_HDMIRX1_FRL_CTRL_CLR_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa929db9fe8649faf5c094fb703fd82f9">XV_HDMIRX1_FRL_CTRL_FLT_CLR_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a32a9590fef5f8526e7c68b2ce8e88f89">XV_HDMIRX1_FRL_CTRL_SET_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#ad8f801766bca274f8235adde45ddc085">XV_HdmiRx1_ConfigFrlLtpDetection()</a>.</p>

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          <td class="memname">int XV_HdmiRx1_RetrieveFrlRateLanes </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function updates the software's FRL Rate and FRL Lanes by reading and decoding the information from the RX core. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Rx core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___frl.html#af43d413c9a668400e3c0b8fbac302e19">XV_HdmiRx1_Frl::CurFrlRate</a>, <a class="el" href="struct_x_v___hdmi_rx1___frl.html#a5e7fe7b2df2ad8498ac0605f9c8de79b">XV_HdmiRx1_Frl::Lanes</a>, <a class="el" href="struct_x_v___hdmi_rx1___frl.html#aa021105f3952e9e9736f572d7eaf2639">XV_HdmiRx1_Frl::LineRate</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#adf8543d358aeaf359d915412003845e3">XV_HdmiRx1::Stream</a>, and <a class="el" href="xv__hdmirx1_8h.html#a38c0efa82d512c42b07775e36f919bb2">XV_HdmiRx1_FrlDdcReadField()</a>.</p>

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        <tr>
          <td class="memname">int XV_HdmiRx1_SelfTest </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function reads ID of PIO peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the HDMI RX core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if PIO ID was matched.</li>
<li>XST_FAILURE if PIO ID was mismatched.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a090582e52a472f924918d70505f62b11">XV_HDMIRX1_MASK_16</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#aa303f116af14392fe13aebd0cc78a125">XV_HDMIRX1_PIO_ID</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#af194c444b1a273aed3950eca10ca1135">XV_HDMIRX1_PIO_ID_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a44f9bde6a5097e3b1c287447e8292f87">XV_HDMIRX1_SHIFT_16</a>.</p>

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          <td class="memname">void XV_HdmiRx1_SetAxiClkFreq </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>ClkFreq</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function sets the AXI4-Lite Clock Frequency. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance. </td></tr>
    <tr><td class="paramname">ClkFreq</td><td>specifies the value that needs to be set.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>This is required after a reset or init. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>.</p>

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          <td class="memname">int XV_HdmiRx1_SetCallback </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942">XV_HdmiRx1_HandlerType</a>&#160;</td>
          <td class="paramname"><em>HandlerType</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>CallbackFunc</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>CallbackRef</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function installs an asynchronous callback function for the given HandlerType: </p>
<pre>
HandlerType                 Callback Function Type
-------------------------   -----------------------------------------------
(XV_HDMIRX1_HANDLER_VTD)      VtdCallback
(XV_HDMIRX1_HANDLER_AUX)      AuxCallback
(XV_HDMIRX1_HANDLER_AUD)      AudCallback
(XV_HDMIRX1_HANDLER_LNKSTA)   LnkStaCallback
(XV_HDMIRX1_HANDLER_PIO)      PioCallback
</pre><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the HDMI RX core instance. </td></tr>
    <tr><td class="paramname">HandlerType</td><td>specifies the type of handler. </td></tr>
    <tr><td class="paramname">CallbackFunc</td><td>is the address of the callback function. </td></tr>
    <tr><td class="paramname">CallbackRef</td><td>is a user data item that will be passed to the callback function when it is invoked.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if callback function installed successfully.</li>
<li>XST_INVALID_PARAM when HandlerType is invalid.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Invoking this function for a handler that already has been installed replaces it with the new handler. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1.html#ac6cde43853e1f68b75e12786b8b27184">XV_HdmiRx1::AudCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a1437670a5591185f97818f3142125a6a">XV_HdmiRx1::AudRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a03b60e69b1ded28e64fc01497d9ea02c">XV_HdmiRx1::AuxCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a1a95fde6db20db59e7466c0115e37776">XV_HdmiRx1::AuxRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a95326a1d0652b0a4d7132fadae0f6137">XV_HdmiRx1::BrdgOverflowCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a48c47143f74cb7ede8f6b0c75036a3a9">XV_HdmiRx1::BrdgOverflowRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ab71556ccd55ddd82fd84890c4e09df18">XV_HdmiRx1::ConnectCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a2204a595a431c54a251c769db17a999a">XV_HdmiRx1::ConnectRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#af1a889495687e670d6a591170761a810">XV_HdmiRx1::DdcCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ab456e187a16c385d672de54131b93f90">XV_HdmiRx1::DdcRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a461b3155ea38ff477c980d26d4ddf905">XV_HdmiRx1::DSCPktErrCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a7c0c69cff125b9c6e4c6fba569c2d22a">XV_HdmiRx1::DSCPktErrRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a0040e6693bb285f67d2065bcc075a2ac">XV_HdmiRx1::DSCStreamChangeEventCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a03a309e3b323da4d94ee94824faeed19">XV_HdmiRx1::DSCStrmChgEvtRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a85040e21167e60e11b8e65e44b3b4bca">XV_HdmiRx1::DSCStsUpdtEvtCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a320629fe5bc5b6be1799ffef48a6c381">XV_HdmiRx1::DSCStsUpdtEvtRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ad47ac62d79ebd12ab76bfefb060618ee">XV_HdmiRx1::DynHdrCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aede71d34c986bdd7d983781514628adb">XV_HdmiRx1::DynHdrRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ad3c15f528662fba6efbc2bf5a1d034a0">XV_HdmiRx1::FrlConfigCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a045d59565efbaaaafe3bf08e390b06df">XV_HdmiRx1::FrlConfigRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#acaf3fc47be10a48fb436adde7c9ffe58">XV_HdmiRx1::FrlLts1Callback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a2da357b5b81ee38779a10e67ba937c3c">XV_HdmiRx1::FrlLts1Ref</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#abd8b1c0fa0acbb9ad46cd09b3d4a0d99">XV_HdmiRx1::FrlLts2Callback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#acd295344643e76e6ff06cb5812797af8">XV_HdmiRx1::FrlLts2Ref</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a881b1b4b7467f5fc289192a357740fa2">XV_HdmiRx1::FrlLts3Callback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ae7b3ce31c2c86f1de1264f29b217c36c">XV_HdmiRx1::FrlLts3Ref</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a26cc49e1c6951045fc6ae64f712c3df3">XV_HdmiRx1::FrlLts4Callback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a6ae119bce17dd8d92a75da04c3ee13b6">XV_HdmiRx1::FrlLts4Ref</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ac4de793fc73dc05c289741273b32aecf">XV_HdmiRx1::FrlLtsLCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a00f9a5251e38ae3078fddceaccfeb1b7">XV_HdmiRx1::FrlLtsLRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a1794a6bc75d1df7be1350f05da38bd5a">XV_HdmiRx1::FrlLtsPCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a538a25be3405a85a5460b734347b8a02">XV_HdmiRx1::FrlLtsPRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a287b6bb5e1ca228324f5126907f03a6c">XV_HdmiRx1::FrlStartCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a52fa0229e234c0e486516cd77c401158">XV_HdmiRx1::FrlStartRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a615c9adae118c4977f069fa964b23ec7">XV_HdmiRx1::Hdcp14ProtEvtCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#acfc764778d0fa356707e6c889ad1074b">XV_HdmiRx1::Hdcp14ProtEvtRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#acca2ad601e630bfc103ee20f84bca196">XV_HdmiRx1::Hdcp22ProtEvtCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ac0b21967ff292888ddba69a22afbd512">XV_HdmiRx1::Hdcp22ProtEvtRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a332b700f16b8e3826767971c3bf859b2">XV_HdmiRx1::HdcpCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ae0248f4981813e9e7d4556a02608a371">XV_HdmiRx1::HdcpRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a6389ceb5ffcc260ea4e14df3b8488d45">XV_HdmiRx1::LinkErrorCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a20bd455b2823281ce7b1280918c1b4a7">XV_HdmiRx1::LinkErrorRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a43745815e66d46ee98ac387d5632dd59">XV_HdmiRx1::LnkRdyErrorCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a96e3091f88f9ac87639a4a49b6a9beb4">XV_HdmiRx1::LnkRdyErrorRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a65bf83a0a4a7289ed9b2b4ce701ac8dd">XV_HdmiRx1::LnkStaCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a301381e0ce61263a70402d8aeda125c3">XV_HdmiRx1::LnkStaRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aee0b055b6e7208d61012abdae2df5018">XV_HdmiRx1::ModeCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a22ce5ab7c1a28b239ef7ee600878fc7d">XV_HdmiRx1::ModeRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ab7df9f45764e36ab61362f08614461d5">XV_HdmiRx1::PhyResetCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ae134dc0565019f363f41fcb807a2e4c9">XV_HdmiRx1::PhyResetRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#af443be7c12d12012fca97167a7326987">XV_HdmiRx1::SkewLockErrorCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#acee2ca9a70528aca2c05758a09369b10">XV_HdmiRx1::SkewLockErrorRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a4e92779a4947b7ff5ec5ea6fe0c0417c">XV_HdmiRx1::StreamDownCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aca26516c2edc8f4444b8fd8e76cf708d">XV_HdmiRx1::StreamDownRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ae72087cc837d809b1beaa9d8b798c9db">XV_HdmiRx1::StreamInitCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a1822f0c9b36e696bcd114f507fdcacb4">XV_HdmiRx1::StreamInitRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a54c1ff6cbf1c7d1c8a7e0323e60d64b6">XV_HdmiRx1::StreamUpCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a337f1873f231c868d157cfdab5943951">XV_HdmiRx1::StreamUpRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a81e87ae653cb737329383942f3d51df5">XV_HdmiRx1::SyncLossCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a65f2508def568fbe0535cd84bb08e4e4">XV_HdmiRx1::SyncLossRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a2838b98abee66bedb928f74f015fd40e">XV_HdmiRx1::TmdsClkRatioCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#adce6045a098ae474c0012cd69d97d402">XV_HdmiRx1::TmdsClkRatioRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ae6f5c0eabdc405e9ee6cbfd455873587">XV_HdmiRx1::TmdsConfigCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa4779228d1c129018101c6e999ae64d6">XV_HdmiRx1::TmdsConfigRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aeef215574a46912f00d61af2f30055e5">XV_HdmiRx1::VfpChangeCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa5cf30103299a7543dfc050f0ca641b5">XV_HdmiRx1::VfpChangeRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ad4b2554e9c12491d37726572f5d64c00">XV_HdmiRx1::VicErrorCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a340c1eb5978cde865536cec3602cec5a">XV_HdmiRx1::VicErrorRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#ab8c7c44a510e8126cf32e22a000c6e84">XV_HdmiRx1::VidRdyErrorCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a507c3a13f898da8f7c514bd94cd7b1f0">XV_HdmiRx1::VidRdyErrorRef</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a8a0bd536ae954e93e6fa5a4f03ee879c">XV_HdmiRx1::VrrRdyCallback</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#a23a3272462cf4e0d6af2e86f8c4e6802">XV_HdmiRx1::VrrRdyRef</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942aa481e1b0c381c69e68f4a336c4f4291a">XV_HDMIRX1_HANDLER_AUD</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942adc98639f1c812cd5a2a72f8cac74c868">XV_HDMIRX1_HANDLER_AUX</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942aebb0160b6b43a4f4e859f45e017faa34">XV_HDMIRX1_HANDLER_BRDG_OVERFLOW</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a9b4c4aa468273738a419e39c05f0baad">XV_HDMIRX1_HANDLER_CONNECT</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942aff8d61798f42199bedb5c4ccce598ff2">XV_HDMIRX1_HANDLER_DDC</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942aa0db97ee67a4f31597b3418b6e988338">XV_HDMIRX1_HANDLER_DDC_HDCP_14_PROT</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942aa9498efdb463dd326e02e578db4e6871">XV_HDMIRX1_HANDLER_DDC_HDCP_22_PROT</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942abd439ec152f3be928e4b1a78f6e462f8">XV_HDMIRX1_HANDLER_DSC_PKT_ERR</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942ae440e854baa6be9065fa24b541a211a8">XV_HDMIRX1_HANDLER_DSC_STRM_CH</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a7e57e5a185607118363c0a8d86b20c6d">XV_HDMIRX1_HANDLER_DSC_STS_UPDT</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a6c6dec8c2000bd56980e104718de20b8">XV_HDMIRX1_HANDLER_DYN_HDR</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942aff9bf32f7a33b804800d8d5706986fd9">XV_HDMIRX1_HANDLER_FRL_CONFIG</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942ab0d40648a4270a90b8816085080c2dc4">XV_HDMIRX1_HANDLER_FRL_START</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a712a8fe2d8cbaa4d6f30a9a34844f1d9">XV_HDMIRX1_HANDLER_HDCP</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a39fd4542c7878df53d3bf3d18d6762a2">XV_HDMIRX1_HANDLER_LINK_ERROR</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a03722585c04e5e62c80b912854856f31">XV_HDMIRX1_HANDLER_LNK_RDY_ERR</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a7a01589f01cadd752b2d205f643756b8">XV_HDMIRX1_HANDLER_LNKSTA</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942ae118085eb55b228455f78663cb661a27">XV_HDMIRX1_HANDLER_MODE</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a6ab6e9177942ae3f4bd6ed8bfa5873b6">XV_HDMIRX1_HANDLER_PHY_RESET</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a9f4c993efb8541e185ba312968e89d93">XV_HDMIRX1_HANDLER_SKEW_LOCK_ERR</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a0433f28ecdfbbaa25be35be1a1864320">XV_HDMIRX1_HANDLER_STREAM_DOWN</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a4759661b3e3b5ec737b4f42194e1c102">XV_HDMIRX1_HANDLER_STREAM_INIT</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a79eb6929b21502e375b3621268df1ead">XV_HDMIRX1_HANDLER_STREAM_UP</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942af9cf2bdb04e25e90100885f80be68d12">XV_HDMIRX1_HANDLER_SYNC_LOSS</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a2c3b39213e1ef49751a14777963398d5">XV_HDMIRX1_HANDLER_TMDS_CLK_RATIO</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a19d8897bb48beef6cc192dce8e656224">XV_HDMIRX1_HANDLER_TMDS_CONFIG</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a9b60139f3a0336b0e920ab5dd18dc183">XV_HDMIRX1_HANDLER_VFP_CHANGE</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a314a6cd00e81397687bdda8b4f073768">XV_HDMIRX1_HANDLER_VIC_ERROR</a>, <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a73d3498284bf4989a39e48a55146abf3">XV_HDMIRX1_HANDLER_VID_RDY_ERR</a>, and <a class="el" href="xv__hdmirx1_8h.html#abbfb262ec57764dd666d070dbda26942a19a71662e67c08479b6f24a6c6930be7">XV_HDMIRX1_HANDLER_VRR_RDY</a>.</p>

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          <td class="memname">void XV_HdmiRx1_SetColorFormat </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
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<p>This function sets the color format. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#adf8543d358aeaf359d915412003845e3">XV_HdmiRx1::Stream</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a686038ae877f6ad613ca1eb8d6e20596">XV_HDMIRX1_PIO_OUT_COLOR_SPACE_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ab91524f2e3868ea812c5e9a6e6a877ec">XV_HDMIRX1_PIO_OUT_COLOR_SPACE_SHIFT</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#acdedab9c5aa955316fd71fcf8597ba83">XV_HDMIRX1_PIO_OUT_MSK_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a2762aba9d45253971668c25e35400e3f">XV_HDMIRX1_PIO_OUT_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiRx1_SetFrl10MicroSecondsTimer </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function sets the timer of RX Core's FRL peripheral for 10 Microseconds. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Rx core instance.</td></tr>
    <tr><td class="paramname">None.</td><td></td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, and <a class="el" href="xv__hdmirx1_8h.html#aaa7bbaf2ae1157d275c4963c2f11cd16">XV_HdmiRx1_Tmr1Start</a>.</p>

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          <td class="memname">void XV_HdmiRx1_SetFrlLtpDetection </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Lane</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XV_HdmiRx1_FrlLtpType&#160;</td>
          <td class="paramname"><em>Ltp</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function sets the link training pattern to be detected for the selected lane. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
    <tr><td class="paramname">Lane</td><td>specifies the lane of which the Link Training Pattern will be detected for.</td></tr>
    <tr><td class="paramname">Ltp</td><td>specifies Link Training Pattern<ul>
<li>5 = LTP5 / LFSR 0</li>
<li>6 = LTP6 / LFSR 1</li>
<li>7 = LTP7 / LFSR 2</li>
<li>8 = LTP8 / LFSR 3</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmirx1_8h.html#ab17e4f96ebbe6785b411233165de859a">XV_HdmiRx1_FrlDdcWriteField()</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#ad8f801766bca274f8235adde45ddc085">XV_HdmiRx1_ConfigFrlLtpDetection()</a>.</p>

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          <td class="memname">void XV_HdmiRx1_SetFrlLtpThreshold </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Threshold</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function sets the number of times the full link training patterns need to be matched before it is considered as a lock. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
    <tr><td class="paramname">Threshold</td><td>specifies the number of times the full link training patterns need to be matched.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#afa179bd6d9cac676f9b7df1ee8ffd205">XV_HDMIRX1_FRL_CTRL_FLT_THRES_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a6bc624e0b0602449534d016b66261420">XV_HDMIRX1_FRL_CTRL_FLT_THRES_SHIFT</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a75abb8243e3ab51c5be8507ea4e3dec8">XV_HDMIRX1_FRL_CTRL_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#a07be19e39e2a3e90ea9ac937f6adfc58">XV_HdmiRx1_FrlLinkRetrain()</a>, and <a class="el" href="xv__hdmirx1__frl_8c.html#a8b8df1df4274fd34afc6ad600c4d1605">XV_HdmiRx1_FrlModeEnable()</a>.</p>

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          <td class="memname">void XV_HdmiRx1_SetFrlRateWrEvent_En </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function sets the FRL rate write enable Event. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a529c5fbb5a5dbc3e6b133550576b915d">XV_HDMIRX1_FRL_CTRL_FRL_RATE_WR_EVT_EN_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a32a9590fef5f8526e7c68b2ce8e88f89">XV_HDMIRX1_FRL_CTRL_SET_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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          <td class="memname">int XV_HdmiRx1_SetHpd </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>SetClr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function enables/clear Hot-Plug-Detect. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance. </td></tr>
    <tr><td class="paramname">SetClr</td><td>specifies TRUE/FALSE value to either enable or clear HPD respectively.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS is always returned.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1_8h.html#a04b941fdfc281d7d81665d47ac32f1d2">XV_HdmiRx1_FrlReset()</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ad0879431e9c01049409338523d61c179">XV_HDMIRX1_PIO_OUT_HPD_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

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          <td class="memname">void XV_HdmiRx1_SetPixelClk </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function sets the PixelClk based on the current ColorDepth, RefClk and ColorFormatId. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1.html#adf8543d358aeaf359d915412003845e3">XV_HdmiRx1::Stream</a>.</p>

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          <td class="memname">int XV_HdmiRx1_SetPixelRate </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
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<p>This function sets the pixel rate. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS is always returned.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1___config.html#ab0d9f429af93cfc3bf3a97e5fc63692c">XV_HdmiRx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="struct_x_v___hdmi_rx1.html#adf8543d358aeaf359d915412003845e3">XV_HdmiRx1::Stream</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#acdedab9c5aa955316fd71fcf8597ba83">XV_HDMIRX1_PIO_OUT_MSK_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a2762aba9d45253971668c25e35400e3f">XV_HDMIRX1_PIO_OUT_OFFSET</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a478987cdc818e2083db0f500ef6b66ab">XV_HDMIRX1_PIO_OUT_PIXEL_RATE_MASK</a>, <a class="el" href="xv__hdmirx1__hw_8h.html#a3177edd91ed0cd44227a908abcd854ca">XV_HDMIRX1_PIO_OUT_PIXEL_RATE_SHIFT</a>, and <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#adca7f7b2b7849037460f1d95faa9ac7a">XV_HdmiRx1_SetStream()</a>.</p>

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          <td class="memname">int XV_HdmiRx1_SetStream </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XVidC_PixelsPerClock&#160;</td>
          <td class="paramname"><em>Ppc</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Clock</em>&#160;</td>
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        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function sets the HDMI RX stream parameters. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance. </td></tr>
    <tr><td class="paramname">Ppc</td><td>specifies the pixel per clock.<ul>
<li>4 = XVIDC_PPC_4 </li>
</ul>
</td></tr>
    <tr><td class="paramname">Clock</td><td>specifies reference pixel clock frequency.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS is always returned.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1.html#adf8543d358aeaf359d915412003845e3">XV_HdmiRx1::Stream</a>, and <a class="el" href="xv__hdmirx1_8c.html#a8a1adaddc73691394f2f181411fffdc7">XV_HdmiRx1_SetPixelRate()</a>.</p>

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          <td class="memname">void XV_HdmiRx1_SetVrrIfType </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XV_HdmiC_VrrInfoframeType&#160;</td>
          <td class="paramname"><em>Type</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>This function Sets VRR infoframe type. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmiRx1 core instance. </td></tr>
    <tr><td class="paramname">Type</td><td>of type XV_HdmiRx1_VrrInfoframeType</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1.html#a815bc83c2185567b85fc6e6261af9d8c">XV_HdmiRx1::VrrIF</a>.</p>

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          <td class="memname">void XV_HdmiRx1_Start </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function starts the HDMI RX core. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This is required after a reset or initialization. </dd></dl>

<p>References <a class="el" href="xv__hdmirx1_8h.html#ab1af2cce1f2ff3ae52dfb4cfbcd9a436">XV_HdmiRx1_PioEnable</a>, and <a class="el" href="xv__hdmirx1_8h.html#a5ec3cb1a32c4e030d365023832bba3e2">XV_HdmiRx1_PioIntrEnable</a>.</p>

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          <td class="memname">void XV_HdmiRx1_Stop </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function stops the HDMI RX core. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmirx1_8h.html#a4d57a91b21377a43a2692f64564bc121">XV_HdmiRx1_PioDisable</a>, and <a class="el" href="xv__hdmirx1_8h.html#ae5f391082b5e60a7ea25086124900070">XV_HdmiRx1_PioIntrDisable</a>.</p>

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          <td class="memname">void XV_HdmiRx1_TmrStartMs </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Milliseconds</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>TimerSelect</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>This function sets the timer of RX Core. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Rx core instance.</td></tr>
    <tr><td class="paramname">Milliseconds</td><td>specifies the timer's frequency (in milliseconds)</td></tr>
    <tr><td class="paramname">TimerSelect</td><td>selects which of the timer unit to be used</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1.html#aa1008eb31826031b552c087c5f8d87d8">XV_HdmiRx1::Config</a>, <a class="el" href="xv__hdmirx1_8h.html#aaa7bbaf2ae1157d275c4963c2f11cd16">XV_HdmiRx1_Tmr1Start</a>, <a class="el" href="xv__hdmirx1_8h.html#ab2b8c0c606b059fe056a78b9a93417b8">XV_HdmiRx1_Tmr2Start</a>, <a class="el" href="xv__hdmirx1_8h.html#a0b54de6bbd95ea2f25998c28db0fef69">XV_HdmiRx1_Tmr3Start</a>, and <a class="el" href="xv__hdmirx1_8h.html#a4de4494c309d24995f84a567459d7b31">XV_HdmiRx1_Tmr4Start</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#adebf854f66fb92c37366faab549dd4a8">XV_HdmiRx1_PhyResetPoll()</a>.</p>

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          <td class="memname">void XV_HdmiRx1_UpdateEdFlags </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_rx1.html">XV_HdmiRx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function checks if RX's CED or RSED counters are incrementing at the rate of 4 or higher per second or if they first hit the maximum value (0x7FFF) then set the CED_Update or RSED_Update SCDC flags if true. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_rx1.html" title="The XHdmiRx1 driver instance data. ">XV_HdmiRx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function needs to be called every 1 second to comply with the spec on CED_Update and RSED_Update flags updating. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_rx1.html#adf8543d358aeaf359d915412003845e3">XV_HdmiRx1::Stream</a>, <a class="el" href="xv__hdmirx1_8h.html#a38c0efa82d512c42b07775e36f919bb2">XV_HdmiRx1_FrlDdcReadField()</a>, and <a class="el" href="xv__hdmirx1_8h.html#ab17e4f96ebbe6785b411233165de859a">XV_HdmiRx1_FrlDdcWriteField()</a>.</p>

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